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1. 发明授权

US06870928B1 Line interface, apparatus and method for coupling transceiver and transmission line 失效
标题翻译：用于耦合收发器和传输线的线路接口，设备和方法
公开(公告)号：US06870928B1
公开(公告)日：2005-03-22
申请号：US09866525
申请日：2001-05-25
申请人： Cormac S. Conroy , Samuel W. Sheng , Ara Bicakci , John DeCelles , Sang-Soo Lee
发明人： Cormac S. Conroy , Samuel W. Sheng , Ara Bicakci , John DeCelles , Sang-Soo Lee
IPC分类号： H04L25/02 , H04L27/00 , H04M1/738 , H04M11/06 , H04M1/00
CPC分类号： H04L27/0002 , H04L25/0266 , H04M1/738 , H04M11/062
摘要： A line interface couples signals between a data transceiver and a transmission line having a load impedance Z. The line interface includes a transformer, a driver circuit for supplying a transmit signal from the data transceiver to the transformer, and a receiver circuit for receiving a receive signal from the transformer. The transformer includes a first port coupled to the transmission line, a second port coupled to the driver circuit, a third port coupled to the receiver circuit, a first winding part having a turns ratio of 1: n, where n>1, for coupling the transmit signal from the second port to the first port, and a second winding part having a turns ratio of 1: m, where m
摘要翻译：线路接口在数据收发器和具有负载阻抗Z的传输线之间耦合信号。线路接口包括变压器，用于从数据收发器向变压器提供发送信号的驱动器电路，以及用于接收接收器的接收器电路来自变压器的信号。变压器包括耦合到传输线的第一端口，耦合到驱动器电路的第二端口，耦合到接收器电路的第三端口，具有匝数比为1：n的第一绕组部件，其中n> 1，用于耦合从第二端口到第一端口的发送信号和匝数比为1：m的第二绕组部分，其中m

2. 发明授权

US06724219B1 Amplifier and line driver for broadband communications 有权
标题翻译：用于宽带通信的放大器和线路驱动器
公开(公告)号：US06724219B1
公开(公告)日：2004-04-20
申请号：US09882499
申请日：2001-06-15
申请人： Chun-Sup Kim , Ara Bicakci , Cormac S. Conroy , Sang-Soo Lee
发明人： Chun-Sup Kim , Ara Bicakci , Cormac S. Conroy , Sang-Soo Lee
IPC分类号： H04B303
CPC分类号： H04L25/0278 , H04L1/0001 , H04L25/028
摘要： A line driver for coupling a data transceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes an input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.
摘要翻译：用于将数据收发器耦合到具有匝数比为1：n的变压器的具有负载阻抗的传输线的线路驱动器包括用于从数据收发器接收输入信号电压的输入端口，用于提供输出信号的输出端口变压器的电压和用于放大输入信号电压的放大器电路。放大器电路包括第一输出级，耦合到输出端的第二输出级，耦合到第一输出级的输出电阻，从第一输出级到放大器电路的输入的反馈路径，以及线匹配网络耦合在第一输出级和第二输出级之间，用于补偿负载阻抗的变化，使得线路驱动器的合成输出阻抗基本上与传输线的实际负载阻抗Z匹配。

3. 发明授权

US06498521B1 Dynamic supply control for line driver 有权
标题翻译：线路驱动器的动态电源控制
公开(公告)号：US06498521B1
公开(公告)日：2002-12-24
申请号：US09998671
申请日：2001-11-29
申请人： Ara Bicakci , Sang-Soo Lee , Cormac S. Conroy
发明人： Ara Bicakci , Sang-Soo Lee , Cormac S. Conroy
IPC分类号： H03B100
CPC分类号： H04L25/0266
摘要： A dynamic supply control circuit is provided for a line driver. The line driver has an amplification factor G, receives an input signal voltage, and drives a transmission line having a load RL via a transformer having a turns ratio of 1:n. The circuit includes an input node for receiving an input signal voltage, a supply node for supplying a driving voltage to the line driver, a lift diode coupled between a fixed supply voltage and the supply node, a lift capacitor coupled between the supply node and an output node, and a lift amplifier having the amplification factor G coupled between the input node and the output node. The lift amplifier drives the lift capacitor when the input signal voltage is greater than an input threshold voltage, the input threshold voltage having a value greater than a common mode voltage of the input signal voltage.
摘要翻译：为线路驱动器提供动态电源控制电路。线路驱动器具有放大系数G，接收输入信号电压，并通过匝数比为1：n的变压器驱动具有负载RL的传输线。电路包括用于接收输入信号电压的输入节点，用于向线路驱动器提供驱动电压的电源节点，耦合在固定电源电压和电源节点之间的升压二极管，耦合在电源节点和输出节点和具有耦合在输入节点和输出节点之间的放大因子G的升降放大器。当输入信号电压大于输入阈值电压时，升降放大器驱动提升电容器，输入阈值电压具有大于输入信号电压的共模电压的值。

4. 发明授权

US07020277B1 DSL line interface having low-pass filter characteristic with reduced external components 失效
标题翻译： DSL线路接口具有低通滤波器特性，减少了外部元件
公开(公告)号：US07020277B1
公开(公告)日：2006-03-28
申请号：US10011153
申请日：2001-12-05
申请人： Sang-Soo Lee , Samuel W. Sheng , Cormac S. Conroy
发明人： Sang-Soo Lee , Samuel W. Sheng , Cormac S. Conroy
IPC分类号： H04B1/52
CPC分类号： H04L25/0266
摘要： A line interface couples a data transceiver to a transmission line via a transformer, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range. The line interface includes an input port for receiving an input signal voltage from an analog front end (AFE) chip, an output port, a line driver for amplifying the input signal voltage and supplying a transmit signal to the output port, a line port for sending the transmit signal and receiving a receive signal, termination resistors coupled between the output port and the line port, a receive signal port for supplying the receive signal to the AFE chip, a receive amplifier formed on the AFE chip coupled to the receive signal port, and a bridge network resistively coupling the line port and the output port to the receive signal port, the bridge network having a low-pass filter characteristic.
摘要翻译：线路接口通过变压器将数据收发器耦合到传输线，数据收发器在第一频率范围内传输信号并在第二频率范围内接收信号。线路接口包括用于从模拟前端（AFE）芯片接收输入信号电压的输入端口，输出端口，用于放大输入信号电压并向输出端口提供发送信号的线路驱动器，用于发送发送信号并接收接收信号，耦合在输出端口和线路端口之间的终端电阻器，用于将接收信号提供给AFE芯片的接收信号端口，耦合到接收信号端口的AFE芯片上形成的接收放大器，桥接网络将线路端口和输出端口电阻地耦合到接收信号端口，桥接网络具有低通滤波器特性。

5. 发明授权

US06970515B1 Line driver for asymmetric digital subscriber line system 有权
标题翻译：用于非对称数字用户线系统的线路驱动器
公开(公告)号：US06970515B1
公开(公告)日：2005-11-29
申请号：US09878142
申请日：2001-06-08
申请人： Ara Bicakci , Cormac S. Conroy
发明人： Ara Bicakci , Cormac S. Conroy
IPC分类号： H04B3/00 , H04L25/02
CPC分类号： H04L25/0278 , H04L25/0266
摘要： A line driver couples a data transceiver to a transmission line having a load impedance Z via a transformer with a turns ratio of 1:n, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range different from the first frequency range. The line driver includes an input port for receiving an input signal voltage, an output port for supplying an output signal voltage to the transformer, and a differential amplifier having a low pass filter for amplifying the input signal voltage and outputting an amplified signal voltage. The line driver further includes termination resistors having a resistance Rt, where R t = Z 2 ⁢ n 2 × k ( 0
摘要翻译：线路驱动器将数据收发器通过匝数比为1：n的变压器将数据收发器耦合到具有负载阻抗Z的传输线，数据收发器在第一频率范围内发送信号并且接收与第一频率不同的第二频率范围的信号频率范围。线路驱动器包括用于接收输入信号电压的输入端口，用于向变压器提供输出信号电压的输出端口以及具有用于放大输入信号电压并输出放大信号电压的低通滤波器的差分放大器。线路驱动器还包括具有电阻R t的终端电阻器，其中 $\begin{matrix} < MTR> \\ R=\frac{/ MI>}{2n/>以及用于耦合输出信号的正反馈路径从输出端口到差分放大器的适当节点的电压，使得合成输出阻抗基本上与第二频率范围上的负载阻抗Z匹配。} \end{matrix}$

6. 发明授权

US06215431B1 Droop-free quasi-continuous reconstruction filter interface 有权
标题翻译：无连续准连续重构滤波器接口
公开(公告)号：US06215431B1
公开(公告)日：2001-04-10
申请号：US09323670
申请日：1999-06-01
申请人： Samuel W. Sheng , Cormac S. Conroy
发明人： Samuel W. Sheng , Cormac S. Conroy
IPC分类号： H03M100
CPC分类号： H03M1/0631 , H03H19/004 , H03M1/0614 , H03M1/66
摘要： A reconstruction filter is described. An input is configured to receive an output signal from a digital to analog converter. An input sampling circuit is operative to store a sample of the output signal from the digital to analog converter. An input pulse generating switch that generates a pulse, the energy of the pulse being determined by the sample of the output signal from the digital to analog converter. An amplifier receives the pulse at an amplifier input and provides an output signal at an amplifier output so that an output signal is produced that reduces distortion caused by imperfections in digital to analog converter.
摘要翻译：描述重构滤波器。输入被配置为从数模转换器接收输出信号。输入采样电路用于存储来自数模转换器的输出信号的采样。产生脉冲的输入脉冲发生开关，脉冲的能量由来自数模转换器的输出信号的样本确定。放大器在放大器输入端接收脉冲，并在放大器输出端提供输出信号，从而产生输出信号，减少由数模转换器中的缺陷引起的失真。

7. 发明授权

US06459684B1 Multiplexed codec for an ADSL system 有权
标题翻译：用于ADSL系统的多路复用编解码器
公开(公告)号：US06459684B1
公开(公告)日：2002-10-01
申请号：US09250426
申请日：1999-02-16
申请人： Cormac S. Conroy , Samuel W. Sheng , Gregory T. Uehara
发明人： Cormac S. Conroy , Samuel W. Sheng , Gregory T. Uehara
IPC分类号： H04B320
CPC分类号： H04L5/023
摘要： An ADSL central office transmission system for transmitting downstream DMT signals to a plurality of remote ADSL transceiver is disclosed. The system includes a DMT digital signal transceiver that generates a time division multiplexed digital signal that includes a plurality of DMT signals to be sent on a plurality of ADSL lines. A digital to analog converter converts the time division multiplexed digital signal into a time division multiplexed analog signal that includes a plurality of analog DMT signals. The analog to digital converter has an output that outputs the time division multiplexed analog signal. A switch selectively connects the output of the digital to analog converter to each of a plurality of transmitters. The transmitters are configured to drive the plurality of ADSL lines. Thus, the plurality ADSL lines are driven by the plurality of analog DMT signals.
摘要翻译：公开了一种用于将下行DMT信号发送到多个远程ADSL收发器的ADSL中心局传输系统。该系统包括DMT数字信号收发器，其产生包括要在多条ADSL线路上发送的多个DMT信号的时分复用数字信号。数模转换器将时分多路复用数字信号转换成包括多个模拟DMT信号的时分复用模拟信号。模数转换器具有输出时分复用的模拟信号的输出。开关选择性地将数模转换器的输出连接到多个发射器中的每一个。发射机被配置为驱动多条ADSL线路。因此，多个ADSL线由多个模拟DMT信号驱动。

8. 发明授权

US07276983B2 Frequency synthesizer with on-chip inductor 有权
标题翻译：具有片上电感的频率合成器
公开(公告)号：US07276983B2
公开(公告)日：2007-10-02
申请号：US10940422
申请日：2004-09-13
申请人： Beomsup Kim , Cormac S. Conroy
发明人： Beomsup Kim , Cormac S. Conroy
IPC分类号： H03B5/12
CPC分类号： H03L7/18 , H03B5/1212 , H03B5/1228 , H03B5/1296 , H03B21/02 , H03L7/099 , H03L7/0995
摘要： A system and method are disclosed for generating a synthesized signal. A frequency synthesizer is used. The frequency synthesizer includes an input interface configured to receive an input signal having a reference frequency; a phase locked loop (PLL) coupled to the input interface, having a fractional N configuration and comprises a voltage controlled oscillator; wherein the voltage controlled oscillator is configured to generate the synthesized signal; and the voltage controlled oscillator includes an on-chip inductor.
摘要翻译：公开了一种用于产生合成信号的系统和方法。使用频率合成器。频率合成器包括被配置为接收具有参考频率的输入信号的输入接口; 耦合到所述输入接口的锁相环（PLL），具有分数N配置并且包括压控振荡器; 其中所述压控振荡器被配置为产生所述合成信号; 并且压控振荡器包括片上电感器。

9. 发明授权

US07158760B1 Frequency synthesizer with selectable preconfigured synthesizer characteristics 有权
标题翻译：频率合成器具有可选择的预配置合成器特性
公开(公告)号：US07158760B1
公开(公告)日：2007-01-02
申请号：US10227634
申请日：2002-08-22
申请人： William B. Baringer , Cormac S. Conroy , Sang Oh Lee , Seok Kang , Beomsup Kim
发明人： William B. Baringer , Cormac S. Conroy , Sang Oh Lee , Seok Kang , Beomsup Kim
IPC分类号： H04B1/40 , H04B7/00 , H04B1/18
CPC分类号： H03L7/16
摘要： A system and method are disclosed for configuring a frequency synthesizer in a transceiver. Configuring a frequency synthesizer in a transceiver includes specifying a selection bit sequence wherein the selection bit sequence corresponds to a predetermined combination of transceiver characteristics; determining a plurality of synthesizer configuration parameters using the selection bit sequence; and configuring the frequency synthesizer using the plurality of synthesizer configuration parameters.
摘要翻译：公开了一种用于在收发器中配置频率合成器的系统和方法。在收发器中配置频率合成器包括指定选择位序列，其中选择位序列对应于收发器特性的预定组合; 使用所述选择比特序列确定多个合成器配置参数; 以及使用所述多个合成器配置参数来配置所述频率合成器。

10. 发明授权

US06292125B1 Digital-to-analog converter using weights stored in a weight table 有权
标题翻译：使用权重表中存储的权重的数模转换器
公开(公告)号：US06292125B1
公开(公告)日：2001-09-18
申请号：US09408016
申请日：1999-09-29
申请人： Cormac S. Conroy
发明人： Cormac S. Conroy
IPC分类号： H03M180
CPC分类号： H03M1/1042 , H03M1/74
摘要： A digital-to-analog converter (“DAC”) and method for digital-to-analog conversion is disclosed. The DAC generally comprises a plurality of analog weights, a weight table adapted to store digital sizes of the plurality of analog weights, and a converter for searching for selected weights from the plurality of analog weights using the digital sizes stored in the weight table and for mapping a binary input to the selected analog weights. The digital sizes of all except for at least two of the analog weights are successively approximated using the assigned sizes of at least two of the analog weights. The method for digital-to-analog conversion, comprising receiving the binary input, searching for selected weights from analog weights using a weight table storing digital sizes of the analog weights, mapping the binary input to the selected weights, and outputting a sum of the selected analog weights.
摘要翻译：公开了一种用于数模转换的数模转换器（“DAC”）和方法。 DAC通常包括多个模拟权重，适用于存储多个模拟权重的数字大小的权重表，以及用于使用存储在权重表中的数字大小从多个模拟权重中搜索所选权重的转换器，将二进制输入映射到所选择的模拟权重。使用至少两个模拟权重的分配尺寸，连续逼近除了至少两个模拟权重之外的所有数字大小。一种用于数模转换的方法，包括接收二进制输入，使用存储模拟权重的数字大小的权重表搜索来自模拟权重的选定权重，将二进制输入映射到所选择的权重，并输出选择的模拟重量。

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