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1. 发明授权

US5770508A Method of forming lightly doped drains in metalic oxide semiconductor components 失效
标题翻译：在金属氧化物半导体部件中形成轻掺杂漏极的方法
公开(公告)号：US5770508A
公开(公告)日：1998-06-23
申请号：US868816
申请日：1997-06-04
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66598 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.
摘要翻译：本发明涉及一种在金属氧化物半导体（MOS）部件中形成轻掺杂漏极的方法。该方法包括在具有栅极的硅衬底之上形成第一绝缘层，第二绝缘层和第三绝缘层，蚀刻层以留下栅极侧壁上的L形第一间隔物，然后将第二类型离子掺杂到硅衬底中在L基第一间隔物下面的硅衬底表面中形成第一轻掺杂漏极，在其他地方在硅衬底表面中形成第二轻掺杂漏极，进一步形成第四绝缘体以形成第三间隔物，并且使用第三间隔物，绝缘层和栅极作为掩模，当将第二类型离子掺入硅衬底中时，以便在未被第三间隔物覆盖的硅衬底表面中形成源/漏区。这种方法产生更大的产量并减少来自晶体管部件的泄漏电流。

2. 发明授权

US06277699B1 Method for forming a metal-oxide-semiconductor transistor 失效
标题翻译：金属氧化物半导体晶体管的形成方法
公开(公告)号：US06277699B1
公开(公告)日：2001-08-21
申请号：US09187140
申请日：1998-11-06
申请人： Coming Chen , Wen-Kuan Yeh , Jih-Wen Chou
发明人： Coming Chen , Wen-Kuan Yeh , Jih-Wen Chou
IPC分类号： H01L21335
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28114 , H01L29/4941 , H01L29/7836
摘要： A method for forming a MOS transistor is provided. A gate oxide layer, a polysilicon layer, a barrier layer and a conductive layer are sequentially formed on a provided substrate. A photolithography and etching process is carried out to remove a portion of the conductive layer and a portion of the barrier layer until exposing the polysilicon layer. An ion implantation is performed to form lightly doped regions in the substrate using the remaining conductive layer and the remaining barrier layer as a mask. A spacer is formed on the side-wall of the conductive layer and on the side-wall of the barrier layer. The polysilicon layer and the gate oxide layer, which are in positions other than those of the remaining conductive layer and the spacer, are removed. The remaining conductive layer and the remaining polysilicon layer constitute a gate with an inversed, T-shaped cross-section. Source/drain regions comprising the lightly doped regions are formed in the substrate by ion implantation using the gate structure as a mask.
摘要翻译：提供一种形成MOS晶体管的方法。在所提供的基板上依次形成栅氧化层，多晶硅层，阻挡层和导电层。进行光刻和蚀刻处理以去除导电层的一部分和阻挡层的一部分直到暴露多晶硅层。执行离子注入，以使用剩余的导电层和剩余的阻挡层作为掩模在衬底中形成轻掺杂区域。在导电层的侧壁和阻挡层的侧壁上形成间隔物。除去剩余导电层和间隔物以外的位置的多晶硅层和栅极氧化物层被去除。剩余的导电层和剩余的多晶硅层构成具有反转的T形横截面的栅极。通过使用栅极结构作为掩模的离子注入，在衬底中形成包括轻掺杂区的源/漏区。

3. 发明授权

US5786255A Method of forming a metallic oxide semiconductor 失效
标题翻译：形成金属氧化物半导体的方法
公开(公告)号：US5786255A
公开(公告)日：1998-07-28
申请号：US863426
申请日：1997-05-27
申请人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21/336 , H01L29/417
CPC分类号： H01L29/66583 , H01L29/41775 , H01L29/41783
摘要： A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.
摘要翻译：形成MOS部件的方法提供了在形成栅极和掺杂源极/漏极区域之后，使用化学 - 机械抛光方法沉积并平坦化多晶硅层。所产生的未移动的多晶硅层用作源极/漏极端子。通过这些布置，离子掺杂的源极/漏极区域将具有浅结，但是它们的连接完整性将不会被随后的接触窗蚀刻和金属化处理所影响。此外，用于形成MOS部件的前端工艺提供了良好的平面表面，为后续工艺的性能提供了极大的便利。

4. 发明授权

US5861329A Method of fabricating metal-oxide semiconductor (MOS) transistors with reduced level of degradation caused by hot carriers 失效
标题翻译：制造由热载流子引起的劣化水平的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US5861329A
公开(公告)日：1999-01-19
申请号：US764254
申请日：1996-12-12
申请人： Wen-Kuan Yeh , Coming Chen , Meng-Jin Tsai , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Coming Chen , Meng-Jin Tsai , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/318 , H01L21/336 , H01L29/49 , H01L21/265 , H01L21/31
CPC分类号： H01L29/6659 , H01L21/0217 , H01L21/02247 , H01L21/28176 , H01L21/3185 , H01L29/4983 , H01L29/6656
摘要： A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.
摘要翻译：提供一种制造金属氧化物半导体（MOS）晶体管的方法。该方法特别设计用于降低由热载流子引起的对MOS晶体管的劣化程度。在制造过程中，对晶片施加等离子体处理，以便在覆盖栅极的晶片和在源极/漏极区上的轻掺杂扩散（LDD）区域上形成氮化硅薄层 MOS晶体管。该氮化硅薄层作为阻止热载流子与栅极介电层交叉的阻挡层，从而可以极大地最小化由于与跨越栅极电介质层的热载流子导致的MOS晶体管的劣化。

5. 发明授权

US06177332B1 Method of manufacturing shallow trench isolation 失效
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US06177332B1
公开(公告)日：2001-01-23
申请号：US09208624
申请日：1998-12-08
申请人： Coming Chen , Jih-Wen Chou
发明人： Coming Chen , Jih-Wen Chou
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.
摘要翻译：描述了制造浅沟槽隔离的方法。该方法包括提供具有衬垫氧化物层，掩模层和沟槽的衬底的步骤，其中沟槽穿过掩模层和焊盘氧化物层并进入衬底。衬底氧化物层形成在衬底中的沟槽的侧壁的一部分上。在沟槽中形成与衬底和衬垫氧化物层之间的界面相同的表面水平的硅层，并且在硅层上形成绝缘层。

6. 发明授权

US5950090A Method for fabricating a metal-oxide semiconductor transistor 失效
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US5950090A
公开(公告)日：1999-09-07
申请号：US193217
申请日：1998-11-16
申请人： Coming Chen , Tony Lin , Jih-Wen Chou
发明人： Coming Chen , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/76224 , H01L29/66545 , H01L29/41775
摘要： A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining portion of the conductive layer also fills a free space between the spacers above the interchangeable source/drain regions to form several contact plugs. A dielectric layer is formed over the substrate with second contact plugs, respectively electrically coupled to the gate metal layer and the first contact plugs.
摘要翻译：提供一种用于制造MOS晶体管器件的方法。该方法包括在半导体衬底上顺序形成氧化物层，多晶硅层和覆盖层。对氧化物层，多晶硅层，盖层和衬底进行图案化，在衬底中形成沟槽开口。通过用绝缘材料填充开口形成浅沟槽隔离（STI）结构。通过图案化氧化物层，多晶硅层和盖层，在衬底上形成第一级栅极结构。暴露基板表面上方的STI结构的顶部。进行轻离子注入以形成轻掺杂区域。在STI结构的第一级栅极结构的每个侧壁和每个暴露的侧壁上分别形成几个间隔物。执行重离子注入工艺以在第一级栅极结构的每一侧形成可互换的源/漏区。盖层去除以留下开口。导电层形成在衬底上并被平坦化，使得导电层的剩余部分填充开口以用作栅极金属层。导电层的剩余部分还填充可互换的源极/漏极区之间的间隔物之间的自由空间，以形成多个接触插塞。在基板上形成介电层，第二接触插塞分别电耦合到栅极金属层和第一接触插塞。

7. 发明授权

US06274450B1 Method for implementing metal oxide semiconductor field effect transistor 失效
标题翻译：金属氧化物半导体场效应晶体管的实现方法
公开(公告)号：US06274450B1
公开(公告)日：2001-08-14
申请号：US09398733
申请日：1999-09-17
申请人： Tony Lin , Coming Chen , Jih-Wen Chou
发明人： Tony Lin , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L29/4966 , H01L29/4983 , H01L29/4991 , H01L29/66507 , H01L29/6653 , H01L29/66545
摘要： A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer. Obviously, one main characteristic of the invention is both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide.
摘要翻译：公开了一种用于制造金属氧化物半导体场效应晶体管的方法。金属氧化物半导体场效应晶体管通过具体的制造工艺形成，有效地防止了热损伤的缺点。根据该方法，首先提供基板。第二，在衬底中形成隔离和阱，然后依次在衬底上形成第一介电层，导电层和抗反射涂层。第三，在衬底上形成栅极，然后在衬底中形成源极和漏极，并在衬底上形成间隔物。第四，源极和漏极都被退火，然后在源极和漏极上形成第一自对准硅化物。第五，在基板上形成第二电介质层并进行平面化处理，其中防反射涂层被完全去除并且导电层被部分去除。第六，在导电层上形成第二个自对准硅化物。第七，去除间隔物，并且在衬底中形成卤素和源极漏极延伸。最后，在第二电介质层上形成第三电介质层。显然，本发明的一个主要特征是源极漏极延伸，并且在诸如沉积，退火和形成硅化物的多个热处理之后形成卤素。

8. 发明授权

US06200840B1 Method for producing PMOS devices 有权
标题翻译：制造PMOS器件的方法
公开(公告)号：US06200840B1
公开(公告)日：2001-03-13
申请号：US09344739
申请日：1999-06-25
申请人： Coming Chen , Jih-Wen Chou
发明人： Coming Chen , Jih-Wen Chou
IPC分类号： H01L21338
CPC分类号： H01L29/6659 , H01L21/28247 , H01L29/665
摘要： A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes a semiconductor substrate which is provided and forms a gate oxide layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, pattern transfers onto the photoresist layer after going through an exposure and a development. Furthermore, the gate layer and the gate oxide layer are then etched by using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin nitride oxide (NO, N2O) layer is grown by utilizing rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN). Hereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A TEOS layer and a silicon nitride layer are deposited by using LPCVD, and forming spacers by etching the silicon nitride layer and the TEOS layer. Next, heavily doping of boron ions occurs as well as an annealing process. The final stage is a procedure of forming metal silicides.
摘要翻译：公开了一种防止硼分离和扩散形成PMOS器件的方法。该方法包括半导体衬底，其被设置并在半导体衬底的顶部上形成栅极氧化物层以及栅极层。接下来，在栅极层的顶表面上形成光致抗蚀剂层，此外，在曝光和显影之后，图案转印到光致抗蚀剂层上。此外，通过使用光致抗蚀剂层作为掩模来蚀刻栅极层和栅极氧化物层，之后除去光致抗蚀剂层。接下来，利用快速热氧化（RTO）和快速热氮化（RTN）生长薄氮氧化物（NO，N2O）层。此后，通过进行离子注入形成硼离子浅结的高掺杂漏极区。通过使用LPCVD沉积TEOS层和氮化硅层，并通过蚀刻氮化硅层和TEOS层形成间隔物。接下来，发生硼离子的重掺杂以及退火工艺。最后阶段是形成金属硅化物的过程。

9. 发明授权

US06187645B1 Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation 有权
标题翻译：用于制造能够防止栅极 - 漏极电容并消除禽鸟形成的半导体器件的方法
公开(公告)号：US06187645B1
公开(公告)日：2001-02-13
申请号：US09233354
申请日：1999-01-19
申请人： Tony Lin , Coming Chen , Jih-Wen Chou
发明人： Tony Lin , Coming Chen , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28035
摘要： A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.
摘要翻译：一种半导体器件的制造方法。该方法包括以下步骤：提供其上具有栅极结构的衬底，然后在栅极结构的侧壁上形成偏置间隔物。此后，进行薄氧化物退火操作，然后使用栅极结构和偏移间隔物作为掩模进行第一离子注入，以在衬底中形成轻掺杂的漏极区。随后，在偏置间隔物的外侧壁上形成二次间隔物。最后，使用栅极结构，偏移间隔物和次级间隔物作为掩模进行第二离子注入，以在轻掺杂漏极区内形成源/漏区。

10. 发明授权

US06177336B1 Method for fabricating a metal-oxide semiconductor device 失效
标题翻译：金属氧化物半导体器件的制造方法
公开(公告)号：US06177336B1
公开(公告)日：2001-01-23
申请号：US09187245
申请日：1998-11-06
申请人： Tony Lin , Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
发明人： Tony Lin , Wen-Kuan Yeh , Coming Chen , Jih-Wen Chou
IPC分类号： H01L214763
CPC分类号： H01L29/66545 , H01L29/66537
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing process is performed to expose the insulating layer so that a remaining portion of the conductive layer fills the opening to form together with the polysilicon layer and the oxide layer to serve as an gate structure.
摘要翻译：提供一种制造金属氧化物半导体（MOS）晶体管的方法。该方法具有在半导体衬底上依次形成氧化物层，多晶硅层和覆盖层以形成第一级栅极的步骤。在第一级栅极的每一侧的衬底中形成具有轻掺杂漏极（LDD）结构的可互换的源极/漏极区域。绝缘层形成在衬底上，并被平坦化以使盖层露出。去除暴露的盖层形成暴露多晶硅层的开口。使用绝缘层作为掩模，执行自对准选择性局部注入工艺以在衬底中的氧化物层下方形成阈值电压掺杂区域和抗穿通掺杂区域。导电层形成在衬底上以填充开口。执行化学机械抛光工艺以暴露绝缘层，使得导电层的剩余部分填充开口以与多晶硅层和氧化物层一起形成以用作栅极结构。

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