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1. 发明授权

US06324108B1 Application of external voltage during array VT testing 有权
标题翻译：阵列VT测试期间应用外部电压
公开(公告)号：US06324108B1
公开(公告)日：2001-11-27
申请号：US09667891
申请日：2000-09-22
申请人： Colin S. Bill , Edward V. Bautista, Jr. , Shigekazu Yamada
发明人： Colin S. Bill , Edward V. Bautista, Jr. , Shigekazu Yamada
IPC分类号： G11C700
CPC分类号： G11C29/12
摘要： When an array VT test mode is entered, a predetermined wordline voltage is generated by a wordline voltage supply and supplied to at least one decoder circuit and a voltage control logic circuit. The voltage control logic circuit generates a predetermined control voltage that is directed to the decoder circuits. The predetermined control voltage activates the decoder circuits. A particular decoder circuit is electrically selected to decode at least one respective wordline and transfer the predetermined wordline voltage to the respective wordline. The activated decoder circuits that are not electrically selected are not forward-biased.
摘要翻译：当输入阵列VT测试模式时，由字线电压源产生预定的字线电压，并提供给至少一个解码器电路和电压控制逻辑电路。电压控制逻辑电路产生指向解码器电路的预定控制电压。预定的控制电压激活解码器电路。特定解码器电路被电选择以解码至少一个相应的字线并将预定字线电压传送到相应的字线。没有电选择的激活的解码器电路不是正向偏置的。

2. 发明授权

US06400638B1 Wordline driver for flash memory read mode 有权
标题翻译：用于闪存读取模式的字线驱动程序
公开(公告)号：US06400638B1
公开(公告)日：2002-06-04
申请号：US09680344
申请日：2000-10-05
申请人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
发明人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C8/08
摘要： The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.
摘要翻译：本发明公开了一种在读取模式期间向多个字线提供预定电压作为字线电压的字线电压调节方法和系统。电源电压（Vcc）由字线驱动器电路调节和温度补偿，以提供比电源电压（Vcc）的幅度更低的预定电压。当启动读取操作时，字线驱动器电路由激活电路激活。在读取操作期间，字线驱动器电路在电源电压（Vcc）的变化期间维持预定电压以及由字线驱动器电路提供的工艺负载的变化。

3. 发明授权

US6147906A Method and system for saving overhead program time in a memory device 有权
标题翻译：用于在存储器件中节省开销程序时间的方法和系统
公开(公告)号：US6147906A
公开(公告)日：2000-11-14
申请号：US419695
申请日：1999-10-14
申请人： Colin S. Bill , Shigekazu Yamada
发明人： Colin S. Bill , Shigekazu Yamada
IPC分类号： G11C16/22 , G11C16/30 , G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： The present invention discloses a method for saving overhead programming time in a flash memory. In the preferred embodiment of the invention, a wordline voltage generation circuit and a bitline voltage generation circuit are electrically connected with a comparator circuit. During the programming operation, the comparator circuit compares a wordline programming voltage and a bitline enabling voltage generated by the voltage generation circuits to determine when the programming voltages reach a predetermined voltage level. Once the predetermined voltage level is reached, the comparator circuit sends an output signal to a state machine that initiates programming for at least one cell. The present invention provides advantages over prior methods of programming by reducing the time period that the state machine waits to initiate programming.
摘要翻译：本发明公开了一种在闪速存储器中节省开销编程时间的方法。在本发明的优选实施例中，字线电压产生电路和位线电压产生电路与比较器电路电连接。在编程操作期间，比较器电路比较字线编程电压和由电压产生电路产生的位线使能电压，以确定编程电压何时达到预定电压电平。一旦达到预定的电压电平，比较器电路将一个输出信号发送到启动至少一个单元的编程的状态机。本发明通过减少状态机等待启动编程的时间段来提供优于现有编程方法的优点。

4. 发明授权

US06438041B1 Negative voltage regulation 有权
标题翻译：负电压调节
公开(公告)号：US06438041B1
公开(公告)日：2002-08-20
申请号：US09668100
申请日：2000-09-22
申请人： Shigekazu Yamada , Colin S. Bill
发明人： Shigekazu Yamada , Colin S. Bill
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C5/147 , G11C8/08 , G11C2216/18
摘要： The present invention discloses a voltage regulation method and system that provides a predetermined erase voltage to at least one wordline during a negative gate stress mode. A low-supply voltage negative charge pump is activated to generate a relatively high negative voltage. The relatively high negative voltage is regulated to the predetermined erase voltage by a regulator circuit. Regulation of the relatively high negative voltage is based on a variable reference voltage that is generated by a reference voltage circuit and directed to the regulator circuit. The predetermined reference voltage is capable of being varied within a first predetermined voltage range, thereby varying the predetermined erase voltage. The predetermined erase voltage is transferred to the wordlines by at least one decoder circuit during an erase operation.
摘要翻译：本发明公开了一种电压调节方法和系统，其在负栅极应力模式期间向至少一个字线提供预定的擦除电压。低电压负电荷泵被激活以产生相对较高的负电压。相对高的负电压由调节器电路调节到预定的擦除电压。相对较高的负电压的调节基于由参考电压电路产生且指向调节器电路的可变参考电压。预定的参考电压能够在第一预定电压范围内变化，从而改变预定的擦除电压。在擦除操作期间，至少一个解码器电路将预定的擦除电压传送到字线。

5. 发明授权

US08238165B2 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same 有权
标题翻译：具有共享电源组和使用其的基于处理器的系统的非易失性存储器件和方法中的字线驱动器
公开(公告)号：US08238165B2
公开(公告)日：2012-08-07
申请号：US13007361
申请日：2011-01-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

6. 发明授权

US07920428B2 Methods and apparatuses relating to automatic cell threshold voltage measurement 有权
标题翻译：与自动电池阈值电压测量相关的方法和装置
公开(公告)号：US07920428B2
公开(公告)日：2011-04-05
申请号：US12352147
申请日：2009-01-12
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C29/12005 , G11C29/50004
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells and a bit line pre-charge reference circuit. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a bit line pre-charge reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和装置。测量电路包括内部参考电流发生器，多个存储器单元和位线预充电参考电路。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。参考电流以很大的步长产生，直到比较位线电压和位线预充电参考电压的比较器被切换为止。参考电流然后以小步骤产生电流，直到再次切换比较器。参考电流在10 nA的精度内收敛于存储单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明的实施例的存储器的系统。

7. 发明授权

US07800953B2 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices 有权
标题翻译：用于在编程或擦除非易失性存储器件期间选择性地限制峰值功耗的方法和系统
公开(公告)号：US07800953B2
公开(公告)日：2010-09-21
申请号：US12505909
申请日：2009-07-20
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/0483
摘要： A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array.
摘要翻译：电源电路用于在存储器单元的编程或擦除期间向非易失性存储单元阵列提供具有有限峰值幅度的功率。电源电路包括提供具有预定大小的参考电流的参考电流源。参考电流源耦合到电流发生器，其向阵列提供电流。电流发生器可以使用电流镜，并且它向阵列提供与参考电流具有预定关系的电流。电流发生器由控制电路选择性地使能，使得在阵列中的至少一些存储器单元的编程或擦除期间将电流提供给阵列。

8. 发明申请

US20090238011A1 VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE 有权
标题翻译：内存数据寄存器内的VCC控制
公开(公告)号：US20090238011A1
公开(公告)日：2009-09-24
申请号：US12052271
申请日：2008-03-20
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.
摘要翻译：提供了一种包括耦合到数据寄存器内的第一反相器的限流电路的存储器件。限流电路控制提供给第一反相器的电压，并且可以调整参考电压，使得防止提供给第一反相器的电压降到低于提供给数据寄存器内的第二反相器的电压。存储器件可以包括开关，以允许耦合到限流电路以编程存储器件。

9. 发明申请

US20090180333A1 Semiconductor memory column decoder device and method 有权
标题翻译：半导体存储器列解码器装置及方法
公开(公告)号：US20090180333A1
公开(公告)日：2009-07-16
申请号：US12008417
申请日：2008-01-10
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

10. 发明申请

US20080117686A1 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices 有权
标题翻译：用于在编程或擦除非易失性存储器件期间选择性地限制峰值功耗的方法和系统
公开(公告)号：US20080117686A1
公开(公告)日：2008-05-22
申请号：US11601368
申请日：2006-11-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06 , G11C5/14
CPC分类号： G11C16/30 , G11C16/0483
摘要： A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array.
摘要翻译：电源电路用于在存储器单元的编程或擦除期间向非易失性存储单元阵列提供具有有限峰值幅度的功率。电源电路包括提供具有预定大小的参考电流的参考电流源。参考电流源耦合到电流发生器，其向阵列提供电流。电流发生器可以使用电流镜，并且它向阵列提供与参考电流具有预定关系的电流。电流发生器由控制电路选择性地使能，使得在阵列中的至少一些存储器单元的编程或擦除期间将电流提供给阵列。

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