专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060139994A1 Method of programming, reading and erasing memory-diode in a memory-diode array 有权
标题翻译：在存储二极管阵列中编程，读取和擦除存储二极管的方法
公开(公告)号：US20060139994A1
公开(公告)日：2006-06-29
申请号：US11021958
申请日：2004-12-23
申请人： Colin Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
发明人： Colin Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
IPC分类号： G11C11/36
CPC分类号： G11C11/36
摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

2. 发明授权

US07379317B2 Method of programming, reading and erasing memory-diode in a memory-diode array 有权
标题翻译：在存储二极管阵列中编程，读取和擦除存储二极管的方法
公开(公告)号：US07379317B2
公开(公告)日：2008-05-27
申请号：US11021958
申请日：2004-12-23
申请人： Colin S. Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
发明人： Colin S. Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
IPC分类号： G11C5/06 , G11C17/06
CPC分类号： G11C11/36
摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

3. 发明申请

US20090109598A1 Metal-insulator-metal (MIM) device and method of formation thereof 有权
标题翻译：金属绝缘体金属（MIM）器件及其形成方法
公开(公告)号：US20090109598A1
公开(公告)日：2009-04-30
申请号：US11980213
申请日：2007-10-30
申请人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
发明人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC分类号： H01G4/002 , H01G7/00
CPC分类号： H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.
摘要翻译：在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，首先提供第一电极。在第一电极上设置氧化物层，在氧化物层上设置保护层。提供通过保护层的开口以暴露氧化物层的一部分，氧化层的暴露部分下方的第一电极的一部分被氧化。提供与氧化物层的暴露部分接触的第二电极。在替代实施例中，可以消除初始提供的氧化物层，并且可以在开口中提供绝缘材料的间隔物。

4. 发明授权

US08445913B2 Metal-insulator-metal (MIM) device and method of formation thereof 有权
公开(公告)号：US08445913B2
公开(公告)日：2013-05-21
申请号：US11980213
申请日：2007-10-30
申请人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
发明人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC分类号： H01L29/12
CPC分类号： H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

5. 发明授权

US07646624B2 Method of selecting operating characteristics of a resistive memory device 有权
标题翻译：选择电阻式存储器件的工作特性的方法
公开(公告)号：US07646624B2
公开(公告)日：2010-01-12
申请号：US11590378
申请日：2006-10-31
申请人： Tzu-Ning Fang , Swaroop Kaza , An Chen , Sameer Haddad
发明人： Tzu-Ning Fang , Swaroop Kaza , An Chen , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/52 , H01L27/2409 , H01L27/2436 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.
摘要翻译：在提供电阻存储器件的工作特性的方法中，选择其电极的材料，从而提供器件的选定工作特性。电极的材料可以与电阻式存储器件的绝缘层的材料反应以形成反应层，所选择的操作特性取决于反应层的存在。

6. 发明授权

US07474579B2 Use of periodic refresh in medium retention memory arrays 有权
标题翻译：在介质保留存储器阵列中使用定期更新
公开(公告)号：US07474579B2
公开(公告)日：2009-01-06
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

7. 发明申请

US20080151669A1 USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
标题翻译：在中继记忆阵列中使用周期性刷新
公开(公告)号：US20080151669A1
公开(公告)日：2008-06-26
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

8. 发明授权

US07706168B2 Erase, programming and leakage characteristics of a resistive memory device 有权
标题翻译：电阻式存储器件的擦除，编程和漏电特性
公开(公告)号：US07706168B2
公开(公告)日：2010-04-27
申请号：US11980116
申请日：2007-10-30
申请人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
发明人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.
摘要翻译：本方法提供了电阻式存储器件的退火，从而使得与现有技术方法相比，处于其擦除状态的器件具有大大增加的电阻。退火还规定，与现有技术相比，可以在增加的电位范围内通过施加多个电位中的任何一个来擦除器件。

9. 发明授权

US07564708B2 Method of programming memory device 有权
标题翻译：编程存储器件的方法
公开(公告)号：US07564708B2
公开(公告)日：2009-07-21
申请号：US11633845
申请日：2006-12-05
申请人： Tzu-Ning Fang , Michael VanBuskirk , Swaroop Kaza
发明人： Tzu-Ning Fang , Michael VanBuskirk , Swaroop Kaza
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32
摘要： In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying electrical potential across the electrodes in one direction, and may be programmed in the electronic charge carrier mode by applying electrical potential across electrodes in the opposite direction.
摘要翻译：在具有第一和第二电极以及电极之间的有源和无源层的存储器件中，或者具有第一和第二电极的存储器件以及在电极之间和与电极接触之间的绝缘层，该器件可以通过施加电在一个方向上跨过电极的电位，并且可以通过在相反方向上跨电极施加电位而以电子载流子模式编程。

10. 发明申请

US20090109727A1 Erase, programming and leakage characteristics of a resistive memory device 有权
标题翻译：电阻式存储器件的擦除，编程和漏电特性
公开(公告)号：US20090109727A1
公开(公告)日：2009-04-30
申请号：US11980116
申请日：2007-10-30
申请人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
发明人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.
摘要翻译：本方法提供了电阻式存储器件的退火，从而使得与现有技术方法相比，处于其擦除状态的器件具有大大增加的电阻。退火还规定，与现有技术相比，可以在增加的电位范围内通过施加多个电位中的任何一个来擦除器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式