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    • 5. 发明授权
    • Method and apparatus for dynamic control of talk groups in a wireless network
    • 无线网络中通话组动态控制的方法和装置
    • US06275500B1
    • 2001-08-14
    • US09370539
    • 1999-08-09
    • Edgar Herbert Callaway, Jr.Christopher T. Thomas
    • Edgar Herbert Callaway, Jr.Christopher T. Thomas
    • H04L1242
    • H04W74/06H04W84/18
    • A transceiver device (50) acting as a master (2) among a plurality of communication devices (1 and 12) potentially acting as slaves to the master (2). The transceiver device (50) includes a transmitter (68), a receiver (54) coupled to the transmitter (68), and a processor (58) coupled to the transmitter (68) and the receiver (54). The processor (58) is programmed to poll the slaves at a first interval and then receive a communication request while polling from a first slave of the plurality of communication devices to communicate with at least a second slave of the plurality of communication devices. The master (2) then designates communication parameters for communication between the first slave and at least the second slave and then polls at a re-polling interval the first slave and at least the second slave to confirm the termination of communication between the first slave and at least the second slave.
    • 在可能充当主机(2)的从站的多个通信设备(1和12)中用作主机(2)的收发机设备(50)。 收发器设备(50)包括发射器(68),耦合到发射器(68)的接收器(54)和耦合到发射器(68)和接收器(54)的处理器(58)。 处理器(58)被编程为以第一间隔轮询从站,然后在从多个通信设备中的第一从站轮询时接收通信请求,以与多个通信设备中的至少第二从站通信。 主(2)然后指定用于第一从机和至少第二从机之间的通信的通信参数,然后以重新轮询间隔轮询第一从机和至少第二从机以确认第一从机和第二从机之间的通信的终止 至少第二个奴隶。
    • 6. 发明授权
    • Method and architecture for complex datapath decimation and channel filtering
    • 复杂数据路径抽取和信道过滤的方法和架构
    • US06470365B1
    • 2002-10-22
    • US09378932
    • 1999-08-23
    • Mahibur RahmanChristopher T. Thomas
    • Mahibur RahmanChristopher T. Thomas
    • G06F1710
    • H03H17/0664H03H17/0671H03H2218/04
    • A decimation and channel filter (100 or 23) in an oversampled system includes a combined decimation and channel filtering architecture for simultaneously processing in-phase and quadrature phase complex input signals. A decimation filter (24) of the combined decimation and channel filter provides sampled outputs to a memory (108) to provide an intermediate result (604), which is stored in the memory (108) in a first format (608). A channel filter (26) of the combined decimation and channel filter processes (610) a decimation final result of the decimation filter in a second format in the memory to provide a final result. This architecture minimizes cost and current drain in a complex signal path decimation and channel filtering process. In addition, a channel filtering algorithm is used to ideally minimize current drain by a factor of 2.
    • 过采样系统中的抽取和信道滤波器(100或23)包括用于同时处理同相和正交相位复数输入信号的组合抽选和信道滤波架构。 组合抽取和通道滤波器的抽取滤波器(24)向存储器(108)提供采样输出以提供以第一格式(608)存储在存储器(108)中的中间结果(604)。 组合抽取和通道滤波器的通道滤波器(26)处理(610)存储器中第二格式的抽取滤波器的抽取最终结果,以提供最终结果。 该架构在复杂信号路径抽取和信道滤波过程中最大限度地降低了成本和电流消耗。 此外,使用信道滤波算法将电流消耗理想地最小化为2倍。