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1. 发明授权

US06531410B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 有权
公开(公告)号：US06531410B2
公开(公告)日：2003-03-11
申请号：US09795610
申请日：2001-02-27
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L2131
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

2. 发明授权

US06339559B1 Decode scheme for programming antifuses arranged in banks 失效
标题翻译：用于在银行中排列的编程反熔丝的解码方案
公开(公告)号：US06339559B1
公开(公告)日：2002-01-15
申请号：US09781883
申请日：2001-02-12
申请人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin van Heel
发明人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin van Heel
IPC分类号： G11C1716
CPC分类号： G11C17/16
摘要： Described is an antifuse array comprising a plurality of antifuse elements and a plurality of cell plates. Each of the antifuse elements comprises a programming transistor and one of the cell plates. The programming transistor and the cell plate of each antifuse element are both activated to program the antifuse element. Each of the cell plates is coupled to a portion of the plurality of antifuse elements and to one of a plurality of decode circuits, and the decode circuits selectively activate its coupled cell plate. With a preferred embodiment, a multitude of interconnect lines are connected to the antifuses and in particular, each interconnect line intersects each of the cell plates and is associated with one antifuse in each group of antifuses. With this preferred embodiment, the array of antifuses are decoded by predecoding one of the cell plates by elevating the cell plate voltage from ground to a program voltage, and decoding one of the interconnect lines to program one of the antifuses. The intersection of the cell plate set to a program voltage and the decoded interconnect line results in programming a unique antifuse.
摘要翻译：描述了包括多个反熔丝元件和多个单元板的反熔丝阵列。每个反熔丝元件包括编程晶体管和单元板之一。每个反熔丝元件的编程晶体管和单元板都被激活以对反熔丝元件进行编程。每个单元板耦合到多个反熔丝元件的一部分和多个解码电路中的一个，并且解码电路选择性地激活其耦合的单元板。利用优选实施例，多个互连线连接到反熔丝，并且特别地，每个互连线与每个单元板相交，并且在每组反熔丝组中与一个反熔丝相关联。利用该优选实施例，通过将单元板电压从地面升高到编程电压，对单元板中的一个进行预解码，并解码其中一条互连线以对其中一个反熔丝进行编译，对反熔丝阵列进行解码。单元板设置为编程电压和解码的互连线的交点导致编程独特的反熔丝。

3. 发明授权

US07276775B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 失效
标题翻译：使用镶嵌栅极工艺的本征双栅极氧化物MOSFET
公开(公告)号：US07276775B2
公开(公告)日：2007-10-02
申请号：US10329593
申请日：2002-12-26
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L29/04 , H01L31/036 , H01L27/10 , H01L29/00
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.
摘要翻译：当与包括（a）在结构上形成具有开口的掩模的方法一起使用时，镶嵌或非镶嵌加工，所述开口具有侧壁; （b）通过开口将抑制物质注入所述结构中，以在所述结构中形成抑制区域; 和（c）在所述开口中的结构上生长电介质层，其中抑制区域部分抑制电介质层的生长能够形成半导体结构，例如包括双重厚度介电层的MOSFET或反熔丝。或者，可以通过用有助于电介质层生长的结构中形成增强区的介电生长增强物种代替上述抑制物质来形成双重厚度电介质。

4. 发明授权

US06570806B2 System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor 有权
标题翻译：用于改善DRAM单电池故障定位和模块级柔性修复的系统和方法以及通用激光熔丝/反熔丝锁芯
公开(公告)号：US06570806B2
公开(公告)日：2003-05-27
申请号：US09891025
申请日：2001-06-25
申请人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin Van Heel , Jason Timothy Varricchione
发明人： Claude Louis Bertin , John Atkinson Fifield , Nicholas Martin Van Heel , Jason Timothy Varricchione
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： A universal fuse latch device includes a latch circuit receiving an electrical signal for initializing the latch circuit to a first state; one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state; and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate reading of one of the fuse and anti-fuse type elements. The universal fuse latch device may be part of a programmable fuse bank including a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is programmed in accordance with a priority of legs to be interrogated in the information fuse latches.
摘要翻译：通用熔丝锁存装置包括一个锁存电路，其接收用于将锁存电路初始化为第一状态的电信号; 一个或多个腿连接在锁存节点处，第一腿实现能够将锁存器从第一状态转换到第二状态的熔丝类型元件; 以及包括反熔丝型元件的第二支脚，其中所述熔丝闩锁设置有熔丝电阻跳变点，以确保所述保险丝和反熔丝型元件之一的充分读取。通用熔丝锁定装置可以是可编程熔丝库的一部分，其包括用于将冗余信息存储在存储器系统中并且能够被同时询问的多个信息熔丝锁存器。包括通用熔丝锁存电路的主熔丝控制装置根据要在信息熔丝锁存器中询问的支腿的优先级进行编程。

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