专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06243283B1 Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US06243283B1
公开(公告)日：2001-06-05
申请号：US09589922
申请日：2000-06-07
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： G11C506
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

2. 发明授权

US6141245A Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US6141245A
公开(公告)日：2000-10-31
申请号：US302902
申请日：1999-04-30
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： H01L27/02 , G11C17/16 , H01L25/065 , G11C16/04
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

3. 发明授权

US06219215B1 Chip thermal protection device 有权
标题翻译：芯片热保护装置
公开(公告)号：US06219215B1
公开(公告)日：2001-04-17
申请号：US09303042
申请日：1999-04-30
申请人： Claude Louis Bertin , Erik Leigh Hedberg , Timothy Dooling Sullivan , William Robert Tonti
发明人： Claude Louis Bertin , Erik Leigh Hedberg , Timothy Dooling Sullivan , William Robert Tonti
IPC分类号： H02H300
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T307/25 , H01L2924/00
摘要： A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to destruct a part of the partially exposed/fully exposed conducting line, thus preventing thermal runaway and over-current condition. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer.
摘要翻译：用作集成电子电路的间隙导电结构，其用作电子熔断器件，并且被集成为用于提供过电流和热失控保护的半导体芯片布线的一部分。间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导电线中产生更高的热流，足以破坏部分暴露/完全暴露的导电线的一部分，从而防止热失控和过电流状态。间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。

4. 发明授权

US06239649B1 Switched body SOI (silicon on insulator) circuits and fabrication method therefor 失效
标题翻译：开关体SOI（绝缘体上硅）电路及其制造方法
公开(公告)号：US06239649B1
公开(公告)日：2001-05-29
申请号：US09295124
申请日：1999-04-20
申请人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
发明人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
IPC分类号： G05F302
CPC分类号： H03K19/0027 , H01L29/78606 , H03K2217/0018
摘要： Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.
摘要翻译：具有SOI器件的电路通过用于选择性地将体偏置电压信号连接到SOI器件主体的开关耦合到体偏置电压。 NMOS或PMOS SOI器件用于开关体SOI器件，FET用于开关，SOI器件的栅极端子连接到FET器件。 SOI器件的栅极将FET偏置电压信号的FET开关连接控制到SOI器件以调整SOI器件的阈值。还公开了并入SOI器件的逻辑电路，以及SOI器件的制造工艺。

5. 发明授权

US07276775B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 失效
标题翻译：使用镶嵌栅极工艺的本征双栅极氧化物MOSFET
公开(公告)号：US07276775B2
公开(公告)日：2007-10-02
申请号：US10329593
申请日：2002-12-26
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L29/04 , H01L31/036 , H01L27/10 , H01L29/00
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.
摘要翻译：当与包括（a）在结构上形成具有开口的掩模的方法一起使用时，镶嵌或非镶嵌加工，所述开口具有侧壁; （b）通过开口将抑制物质注入所述结构中，以在所述结构中形成抑制区域; 和（c）在所述开口中的结构上生长电介质层，其中抑制区域部分抑制电介质层的生长能够形成半导体结构，例如包括双重厚度介电层的MOSFET或反熔丝。或者，可以通过用有助于电介质层生长的结构中形成增强区的介电生长增强物种代替上述抑制物质来形成双重厚度电介质。

6. 发明授权

US06943452B2 Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality 失效
标题翻译： SOI半导体内同轴布线，PCB到系统高速运行和信号质量
公开(公告)号：US06943452B2
公开(公告)日：2005-09-13
申请号：US10103297
申请日：2002-03-21
申请人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
发明人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
IPC分类号： H01L21/768 , H01L21/84 , H01L23/66 , H05K1/02 , H05K3/34 , H05K3/46 , H01L23/12 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/0221 , H01L21/84 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01L2924/3011 , H05K3/3436 , H05K3/3447 , H05K3/4644 , H05K2201/09509 , H05K2201/09518 , H05K2201/09809 , H05K2201/09981 , H05K2201/10356 , H05K2201/10674 , H05K2203/061 , H01L2924/00
摘要： An integrated circuit is provided that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.
摘要翻译：提供一种集成电路，其包含至少部分地形成在含硅衬底内的同轴信号线。同轴信号线包括内部导体，其具有沿着所述长度的外部导体的长度，所述长度被轴向包围并绝缘。本文还公开了一种制备具有至少部分地形成在含硅衬底内的所述同轴信号线的集成电路的方法。

7. 发明授权

US06531410B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 有权
公开(公告)号：US06531410B2
公开(公告)日：2003-03-11
申请号：US09795610
申请日：2001-02-27
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L2131
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

8. 发明授权

US06388198B1 Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality 失效
标题翻译： SOI半导体内同轴布线，PCB到系统高速运行和信号质量
公开(公告)号：US06388198B1
公开(公告)日：2002-05-14
申请号：US09265098
申请日：1999-03-09
申请人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
发明人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
IPC分类号： H05K109
CPC分类号： H05K1/0221 , H01L21/84 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01L2924/3011 , H05K3/3436 , H05K3/3447 , H05K3/4644 , H05K2201/09509 , H05K2201/09518 , H05K2201/09809 , H05K2201/09981 , H05K2201/10356 , H05K2201/10674 , H05K2203/061 , H01L2924/00
摘要： An integrated circuit that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.
摘要翻译：一种集成电路，其包含至少部分地形成在含硅衬底内的同轴信号线。同轴信号线包括内导体，其具有沿着所述长度的外导体沿轴向包围并绝缘的长度。本文还公开了一种制备具有至少部分地形成在含硅衬底内的所述同轴信号线的集成电路的方法。

9. 发明授权

US06345362B1 Managing Vt for reduced power using a status table 有权
标题翻译：使用状态表管理Vt降低功耗
公开(公告)号：US06345362B1
公开(公告)日：2002-02-05
申请号：US09287173
申请日：1999-04-06
申请人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
发明人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02D10/126 , Y02D10/171
摘要： An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.
摘要翻译：集成电路包括CPU，电源管理单元和专用于执行不同功能的多个功能单元。电源管理单元控制不同功能单元的阈值电压，以优化电路的功率/性能运行，智能电源管理控制响应指令流并依次对每条指令进行解码。该信息识别特定指令需要哪个功能单元，并且通过将该信息与功率状态进行比较，智能功率控制确定执行命令所需的功能单元是否处于最佳功率级。如果是，则允许该命令继续进行，否则智能功率控制将停止指令序列或修改处理速度。

10. 发明授权

US06693843B1 Wordline on and off voltage compensation circuit based on the array device threshold voltage 有权
标题翻译：基于阵列器件阈值电压的字线开关电压补偿电路
公开(公告)号：US06693843B1
公开(公告)日：2004-02-17
申请号：US10318795
申请日：2002-12-13
申请人： Thomas M. Maffitt , Russell J. Houghton , Mark David Jacunski , William Robert Tonti , Kevin McStay
发明人： Thomas M. Maffitt , Russell J. Houghton , Mark David Jacunski , William Robert Tonti , Kevin McStay
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage (“VT”) monitor, a wordline on voltage (“Vpp”) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (“VWLL”) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.
摘要翻译：提供了一种用于集成存储器中的字线电压补偿的装置和方法，其中装置包括阵列阈值电压（“VT”）监视器，与阈值电压监视器进行信号通信的电压（“Vpp”）发生器的字线，用于提供响应于所监视的阵列阈值电压的变化的字线电压以及与阈值电压监视器进行信号通信的字线关断电压（“VWLL”）发生器，用于响应于所监视的阵列阈值电压的变化提供字线关断电压; 并且其中用于补偿与阵列阈值信号相对应的信号上的字线和字线关闭信号中的每一个的相应方法包括监视阵列阈值信号，响应于所监视的阵列阈值信号产生信号上的字线，并产生字线关闭响应于监视的阵列阈值信号的信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式