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1. 发明授权

US5043778A Oxide-isolated source/drain transistor 失效
标题翻译：氧化物隔离源极/漏极晶体管
公开(公告)号：US5043778A
公开(公告)日：1991-08-27
申请号：US238978
申请日：1988-08-25
申请人： Clarence W. Teng , Thomas E. Tang , Che-Chia Wei
发明人： Clarence W. Teng , Thomas E. Tang , Che-Chia Wei
IPC分类号： H01L21/285 , H01L21/308 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66636 , H01L21/28525 , H01L21/3086 , H01L21/76218 , H01L21/823814 , H01L21/823878 , H01L29/0638 , H01L29/0653 , H01L29/0847 , H01L27/0921 , H01L27/0928 , Y10S257/90
摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.
摘要翻译：具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些通过使用硅蚀刻形成凹槽形成的“源极/漏极”区域36，用氧化物限制蚀刻的凹槽，并且填充与多晶硅。短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。通过该接触的小面积的扩散将在硅中形成小的漫射体44，其作为电学有效的源极/漏极区域。在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

2. 发明授权

US4963502A Method of making oxide-isolated source/drain transistor 失效
标题翻译：制造氧化物隔离源/漏晶体管的方法
公开(公告)号：US4963502A
公开(公告)日：1990-10-16
申请号：US416566
申请日：1989-10-03
申请人： Clarence W. Teng , Thomas E. Tang , Che-Chia Wei
发明人： Clarence W. Teng , Thomas E. Tang , Che-Chia Wei
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66636 , H01L21/28525 , H01L21/823814 , H01L21/823878 , H01L29/0638 , H01L29/0653 , H01L29/0847 , H01L27/0921 , H01L27/0928
摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.
摘要翻译：具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些“源极/漏极”区域36通过使用硅蚀刻形成凹部，用氧化物衬在蚀刻的凹槽上，以及回填多晶硅。短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。通过该接触的小面积的扩散将在硅中形成小的扩散部分44，其作为电有效的源极/漏极区域。在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

3. 发明授权

US4788160A Process for formation of shallow silicided junctions 失效
标题翻译：形成浅层硅化物结的方法
公开(公告)号：US4788160A
公开(公告)日：1988-11-29
申请号：US32836
申请日：1987-03-31
申请人： Robert H. Havemann , Roger A. Haken , Thomas E. Tang , Che-Chia Wei
发明人： Robert H. Havemann , Roger A. Haken , Thomas E. Tang , Che-Chia Wei
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L29/45 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/456 , Y10S148/105 , Y10S148/147 , Y10S438/923
摘要： A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.
摘要翻译：形成浅硅化物结的方法包括在护城河区域上溅射钛（28）层以覆盖形成在栅电极（18）的侧壁上的栅电极（18）和侧壁氧化物（22）的步骤。钛与暴露的硅区（24）和（26）反应以形成硅化物层（30）和（32），然后在汽提未反应的钛之前将掺杂剂杂质注入到衬底（10）中。未反应的钛（36），（38）或（40）起到掩模的作用，以将注入区域从栅电极（18）下方的沟道区域（20）偏移，并且还防止杂质在区域在定义的护城河地区之外。

4. 发明授权

US4975756A SRAM with local interconnect 失效
标题翻译：具有本地互连的SRAM
公开(公告)号：US4975756A
公开(公告)日：1990-12-04
申请号：US317149
申请日：1989-02-28
申请人： Roger A. Haken , Thomas E. Tang , Che-Chia Wei , Larry R. Hite
发明人： Roger A. Haken , Thomas E. Tang , Che-Chia Wei , Larry R. Hite
IPC分类号： H01L21/311 , H01L21/321 , H01L21/768 , H01L21/8238 , H01L21/8247 , H01L27/105 , H01L27/11
CPC分类号： H01L27/11526 , H01L21/31111 , H01L21/31116 , H01L21/3211 , H01L21/76889 , H01L21/76895 , H01L21/823835 , H01L27/105 , H01L27/1108 , H01L27/11543
摘要： An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density.
摘要翻译：使用TiN局部互连的SRAM。这样可以减少护城河寄生电容，并避免使用金属跳线，导致密度增加。

5. 发明授权

US4890141A CMOS device with both p+ and n+ gates 失效
标题翻译：具有p +和n +门的CMOS器件
公开(公告)号：US4890141A
公开(公告)日：1989-12-26
申请号：US214912
申请日：1988-06-29
申请人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Richard A. Chapman
发明人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Richard A. Chapman
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/092 , H01L27/105 , H01L27/11
CPC分类号： H01L27/11526 , H01L21/76895 , H01L27/092 , H01L27/105 , H01L27/1104 , H01L27/1108 , H01L27/11543 , Y10S257/903 , Y10S257/915
摘要： A CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat.
摘要翻译：一种CMOS器件，其中N沟道器件具有n +栅极，并且P沟道器件具有p +栅极。 TiN局部互连系统用于连接两种类型的门，以及提供护城河的连接。

6. 发明授权

US4920073A Selective silicidation process using a titanium nitride protective layer 失效
标题翻译：使用氮化钛保护层的选择性硅化工艺
公开(公告)号：US4920073A
公开(公告)日：1990-04-24
申请号：US350429
申请日：1989-05-11
申请人： Che-Chia Wei , Thomas E. Tang , James G. Bohlman , Monte A. Douglas
发明人： Che-Chia Wei , Thomas E. Tang , James G. Bohlman , Monte A. Douglas
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/321 , H01L21/336 , H01L23/52
CPC分类号： H01L29/665 , H01L21/3211 , Y10S148/113 , Y10S148/147
摘要： The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.
摘要翻译：本发明提供了在钛与集成电路的暴露的硅区域的直接反应期间抑制钛层的氧化的方法。在本发明的一个实施例中，在沉积钛层的反应器中的钛层的表面上形成氮化钛层。氮化钛层提供了抗氧化的有效屏障。因此，二氧化钛的形成被抑制。此外，在要在扩散区域之间形成氮化钛局部互连的区域中，由顶部氮化钛层提供的额外的厚度增加了导电层的完整性。通过在氮化物气氛中进行硅化，氮化物从钛氮化物层扩散到钛层中，并且由于大气中的那些失去的氮原子而被发生，从而提供用于形成硅化钛短路的阻挡层。

7. 发明授权

US5166770A Silicided structures having openings therein 失效
标题翻译：其中有开孔的硅化结构
公开(公告)号：US5166770A
公开(公告)日：1992-11-24
申请号：US38394
申请日：1987-04-15
申请人： Thomas E. Tang , Che-Chia Wei , Cheng-Eng D. Chen
发明人： Thomas E. Tang , Che-Chia Wei , Cheng-Eng D. Chen
IPC分类号： H01L21/285 , H01L21/8238 , H01L23/532 , H01L27/092 , H01L29/78
CPC分类号： H01L21/285 , H01L23/53257 , H01L27/0928 , H01L2924/0002
摘要： Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.
摘要翻译：优选实施例包括具有钛硅化物结（38,58）的硅互补MOSFET和铝金属化（61,62）与p结（58）的直接接触，避免了硅化物（60）对p硅（58）的高接触电阻）。优选实施例还包括没有相应的硅化MOSFET结的硅化多晶硅线。

8. 发明授权

US4690730A Oxide-capped titanium silicide formation 失效
标题翻译：氧化物封端的硅化钛形成
公开(公告)号：US4690730A
公开(公告)日：1987-09-01
申请号：US876947
申请日：1986-06-20
申请人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Thomas C. Holloway , David A. Bell
发明人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Thomas C. Holloway , David A. Bell
IPC分类号： H01L21/28 , H01L21/283 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L23/52 , H01L29/78 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L29/6659 , H01L21/28518 , H01L21/76895 , H01L2924/0002
摘要： A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.
摘要翻译：氧化物（或氧化物/氮化物）在反应步骤期间防止硅扩散，其形成直接反应的硅化钛。

9. 发明授权

US4676866A Process to increase tin thickness 失效
标题翻译：增加锡厚度的工艺
公开(公告)号：US4676866A
公开(公告)日：1987-06-30
申请号：US837482
申请日：1986-03-07
申请人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Thomas C. Holloway
发明人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Thomas C. Holloway
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8247 , H01L27/105 , H01L27/11 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L27/11526 , H01L21/32053 , H01L21/76895 , H01L27/105 , H01L27/1108 , H01L27/11543
摘要： A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.
摘要翻译：用于VLSI集成电路的局部互连系统。在氮气气氛中暴露的山沟和栅极区域的自对准硅化过程中，整体形成导电氮化钛层。然后将第二钛层整体沉积并再次反应，以增加氮化物层而不增加硅化物层的厚度。对该导电层进行图案化和蚀刻，以提供局部互连，其平面电阻为10欧姆/平方，并且也蚀刻停止。此外，这种局部互连级别允许接触与护城河边界不对准，因为氮化钛局部互连层可以从护壕向上叠加到场氧化物上，以提供用于接触孔的底部接触和扩散屏障通过层间氧化物蚀刻。这种局部互连功能可以满足埋入式接触能力的所有功能，并满足其他功能。

10. 发明授权

US5010032A Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects 失效
$Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects$
标题翻译：用于制造具有P +和N +栅极的CMOS器件的方法，包括难熔金属硅化物和氮化物互连
公开(公告)号：US5010032A
公开(公告)日：1991-04-23
申请号：US417386
申请日：1989-10-05
申请人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Richard A. Chapman
发明人： Thomas E. Tang , Che-Chia Wei , Roger A. Haken , Richard A. Chapman
IPC分类号： H01L21/311 , H01L21/321 , H01L21/768 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/105 , H01L27/11
CPC分类号： H01L27/11526 , H01L21/31111 , H01L21/31116 , H01L21/3211 , H01L21/76889 , H01L21/76895 , H01L21/823835 , H01L27/092 , H01L27/105 , H01L27/1108 , H01L27/11543 , Y10S148/147
摘要： A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.
摘要翻译：一种制造CMOS器件的方法，其中N沟道器件具有n +栅极，并且P沟道器件具有p +栅极。 TiN局部互连系统用于连接两种类型的门，以及提供护城河的连接。可以通过在各处沉积钛金属，然后在氮气气氛中加热集成电路结构来形成氮化钛层。该方法也可以与其它难熔金属氮化物互连层一起使用。除了钛基薄膜组合物之外，其它金属可以被取代并用于直接反应硅化和同时形成导电氮化物以形成局部互连，包括钼，钨，钒，钴等。

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