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1. 发明申请

US20070290227A1 Dual-gate transistor and pixel structure using the same 有权
标题翻译：双栅晶体管和像素结构使用相同
公开(公告)号：US20070290227A1
公开(公告)日：2007-12-20
申请号：US11812002
申请日：2007-06-14
申请人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
发明人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
IPC分类号： H01L29/49
CPC分类号： H01L29/42384 , H01L29/78648 , H01L29/78696
摘要： A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.
摘要翻译：双栅极晶体管包括形成在衬底上的第一栅极，覆盖第一栅极和衬底的第一电介质层，形成在第一电介质层上的半导体层，形成在半导体层上并以间隔隔开的第一和第二电极为了彼此分离，覆盖第一和第二电极的第二电介质层和形成在第二电介质层上的第二栅极，其中第一和第二栅极中的至少一个与第二电极不重叠。

2. 发明授权

US07982268B2 Dual-gate transistor and pixel structure using the same 有权
标题翻译：双栅晶体管和像素结构使用相同
公开(公告)号：US07982268B2
公开(公告)日：2011-07-19
申请号：US11812002
申请日：2007-06-14
申请人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
发明人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
IPC分类号： H01L29/66
CPC分类号： H01L29/42384 , H01L29/78648 , H01L29/78696
摘要： A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.
摘要翻译：双栅极晶体管包括形成在衬底上的第一栅极，覆盖第一栅极和衬底的第一电介质层，形成在第一电介质层上的半导体层，形成在半导体层上并以间隔隔开的第一和第二电极为了彼此分离，覆盖第一和第二电极的第二电介质层和形成在第二电介质层上的第二栅极，其中第一和第二栅极中的至少一个与第二电极不重叠。

3. 发明授权

US08378423B2 Dual-gate transistor and pixel structure using the same 有权
标题翻译：双栅晶体管和像素结构使用相同
公开(公告)号：US08378423B2
公开(公告)日：2013-02-19
申请号：US13071422
申请日：2011-03-24
申请人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
发明人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
IPC分类号： H01L29/66
CPC分类号： H01L29/42384 , H01L29/78648 , H01L29/78696
摘要： A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.
摘要翻译：双栅极晶体管包括形成在衬底上的第一栅极，覆盖第一栅极和衬底的第一电介质层，形成在第一电介质层上的半导体层，形成在半导体层上并以间隔隔开的第一和第二电极为了彼此分离，覆盖第一和第二电极的第二电介质层和形成在第二电介质层上的第二栅极，其中第一和第二栅极中的至少一个与第二电极不重叠。

4. 发明申请

US20110168998A1 DUAL-GATE TRANSISTOR AND PIXEL STRUCTURE USING THE SAME 有权
标题翻译：双门晶体管和像素结构使用相同
公开(公告)号：US20110168998A1
公开(公告)日：2011-07-14
申请号：US13071422
申请日：2011-03-24
申请人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
发明人： Chung-Yu Liang , Feng-Yuan Gan , Ting-Chang Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/42384 , H01L29/78648 , H01L29/78696
摘要： A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spaced with an interval in order to separate each other, a second dielectric layer covering the first and second electrodes, and a second gate formed on the second dielectric layer, in which at least one of the first and second gates is non-overlapped with the second electrode.
摘要翻译：双栅极晶体管包括形成在衬底上的第一栅极，覆盖第一栅极和衬底的第一电介质层，形成在第一电介质层上的半导体层，形成在半导体层上并以间隔隔开的第一和第二电极为了彼此分离，覆盖第一和第二电极的第二电介质层和形成在第二电介质层上的第二栅极，其中第一和第二栅极中的至少一个与第二电极不重叠。

5. 发明申请

US20060124930A1 THIN FILM TRANSISTOR AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20060124930A1
公开(公告)日：2006-06-15
申请号：US10908077
申请日：2005-04-27
申请人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Feng-Yuan Gan
发明人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Feng-Yuan Gan
IPC分类号： H01L31/0376 , H01L29/04
CPC分类号： H01L29/66765 , H01L29/78618 , H01L29/78669
摘要： A thin film transistor is characterized by having an island-in structure having a semiconductor layer with a channel region, a bottom heavily-doped semiconductor layer, and a top heavily-doped semiconductor layer. The bottom heavily-doped semiconductor layer is positioned on two opposite sides of the surface of the semiconductor layer beyond the channel region. The top heavily-doped semiconductor layer, positioned on the bottom heavily-doped semiconductor layer, covers two opposite side walls of the bottom heavily-doped semiconductor layer and the semiconductor layer so that current leakage from the drain electrode to the source electrode is prevented.
摘要翻译：薄膜晶体管的特征在于具有岛状结构，其具有具有沟道区的半导体层，底部重掺杂半导体层和顶部重掺杂半导体层。底部重掺杂半导体层位于超过沟道区的半导体层表面的相对两侧。位于底部重掺杂半导体层上的顶部重掺杂半导体层覆盖底部重掺杂半导体层和半导体层的两个相对的侧壁，从而防止从漏电极到源电极的电流泄漏。

6. 发明授权

US08427879B2 Method for enabling a SONOS transistor to be used as both a switch and a memory 有权
标题翻译：使SONOS晶体管能够用作开关和存储器的方法
公开(公告)号：US08427879B2
公开(公告)日：2013-04-23
申请号：US12644575
申请日：2009-12-22
申请人： Ting-Chang Chang , Shih-Ching Chen , Te-Chih Chen , Fu-Yen Jian , Yong-En Syu
发明人： Ting-Chang Chang , Shih-Ching Chen , Te-Chih Chen , Fu-Yen Jian , Yong-En Syu
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/10 , H01L29/792
摘要： There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.
摘要翻译：存在使SONOS晶体管能够用作开关和存储器的方法。通过晶体管的源极或漏极进行FN隧穿，从而进一步改变存储在与漏极或源极相邻的上部电荷存储层中的电子的状态，并且使用栅极引起的漏极泄漏的变化来识别漏极和源的存储状态。在此操作期间，始终保持晶体管的稳定阈值电压。本发明使得具有开关和存储器的双重特征的单个晶体管同时具有两比特存储器效应，从而与通用晶体管相比提供了更高的存储器密度。

7. 发明授权

US07701007B2 Thin film transistor with source and drain separately formed from amorphus silicon region 有权
标题翻译：源极和漏极的薄膜晶体管分别由非晶硅区域形成
公开(公告)号：US07701007B2
公开(公告)日：2010-04-20
申请号：US11393742
申请日：2006-03-31
申请人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Kuo-Yu Huang , Jen-Chien Peng
发明人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Kuo-Yu Huang , Jen-Chien Peng
IPC分类号： H01L27/12
CPC分类号： H01L29/66765 , H01L27/124 , H01L27/1248
摘要： A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.
摘要翻译：薄膜晶体管包括形成在基板上的栅电极; 覆盖栅电极的栅极绝缘层; 设置在栅极绝缘层上和栅电极上方的非晶硅（a-Si）区; 形成在a-Si区上的掺杂a-Si区; 源极和漏极金属区域分别形成在掺杂的a-Si区域和栅电极上方，并与a-Si区域隔离; 形成在所述栅极绝缘层上并覆盖所述源极，漏极和数据线（DL）金属区域的钝化层; 以及形成在钝化层上的导电层。钝化层具有用于分别暴露源极，漏极和DL金属区域的部分表面的第一，第二和第三通孔。第一，第二和第三通孔填充有导电层，使得DL和源极金属区域经由导电层连接。

8. 发明授权

US07022571B2 Quantum structure and forming method of the same 有权
标题翻译：量子结构和形成方法相同
公开(公告)号：US07022571B2
公开(公告)日：2006-04-04
申请号：US10426873
申请日：2003-05-01
申请人： Ting-Chang Chang , Po-Tsun Liu
发明人： Ting-Chang Chang , Po-Tsun Liu
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , B82Y10/00 , H01L21/28194 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/517
摘要： A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric layer for forming a second dielectric layer thereon. The second dielectric layer has major elements and impurities contained. Treating the second dielectric layer to drive the impurities to form the quantum structure. For example, oxidizing the major elements to drive the impurities in the first dielectric layer to form the quantum structure in said first dielectric layer because the oxidizing capability of the major elements is stronger than that of the impurities.
摘要翻译：提供了基于两个特征的差异的量子结构和形成方法。成型方法包括几个步骤。首先，提供用于在其上形成第二电介质层的第一电介质层。第二电介质层含有主要元素和杂质。处理第二介质层以驱动杂质以形成量子结构。例如，氧化主要元素以驱动第一电介质层中的杂质以在所述第一介电层中形成量子结构，因为主要元素的氧化能力比杂质的氧化能力更强。

9. 发明授权

US06426246B1 Method for forming thin film transistor with lateral crystallization 有权
标题翻译：用横向结晶形成薄膜晶体管的方法
公开(公告)号：US06426246B1
公开(公告)日：2002-07-30
申请号：US09789347
申请日：2001-02-21
申请人： Ting-Chang Chang , Du-Zen Peng , Chun-Yen Chang
发明人： Ting-Chang Chang , Du-Zen Peng , Chun-Yen Chang
IPC分类号： H01L2100
CPC分类号： H01L29/66757 , H01L29/78675
摘要： A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a portion of the amorphous silicon layer by excimer laser system, and the lateral-growth grain is formed by using the seeds to grow laterally by annealing the amorphous silicon layer, wherein the amorphous silicon layer defines an active region. Then, sequentially a dielectric layer and a polysilicon layer is deposited on the active region, wherein the dielectric layer and the polysilicon layer are gate electrodes, a gate is defined on the substrate, and the polysilicon layer is formed by etching. Next, source and drain regions are formed by implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask.
摘要翻译：一种用于形成具有横向结晶的薄膜晶体管的方法。该方法至少包括以下步骤。首先，提供绝缘基板。然后，在绝缘基板上设置非晶硅层。通过准分子激光系统对非晶硅层的一部分进行退火而形成种子，并且通过使晶种通过使非晶硅层退火而横向生长而形成横向生长晶粒，其中非晶硅层限定有源区。然后，依次在有源区上沉积介质层和多晶硅层，其中介质层和多晶硅层是栅电极，在衬底上限定栅极，并且通过蚀刻形成多晶硅层。接下来，通过使用栅电极作为掩模，通过将许多离子注入非晶硅层来形成源区和漏区。

10. 发明授权

US06423652B1 Post-processing treatment of low dielectric constant material 失效
标题翻译：低介电常数材料的后处理处理
公开(公告)号：US06423652B1
公开(公告)日：2002-07-23
申请号：US09420960
申请日：1999-10-19
申请人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
发明人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
IPC分类号： H01L2131
CPC分类号： H01L21/02137 , H01L21/02203 , H01L21/02282 , H01L21/02351 , H01L21/265 , H01L21/3105 , H01L21/3121
摘要： A post-processing treatment of a low dielectric constant material. In the post-processing treatment, a shallow implantation is conducted to form a shallow compact layer over a dielectric film. This shallow compact surface layer acts as a barrier that prevents the absorption of moisture by the dielectric film. The shallow implantation is carried out using boron ions at an energy level of between about 10 and 50 keV and a dosage of between about 1×1015 atm/cm2 and 1×1016 atm/cm2.
摘要翻译：对低介电常数材料进行后处理处理。在后处理处理中，进行浅注入以在电介质膜上形成浅致密层。这种浅的紧密表面层用作防止电介质膜吸收水分的屏障。在约10至50keV的能级和约1×10 15 atm / cm 2和1×10 16 atm / cm 2的剂量之间使用硼离子进行浅注入。

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