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1. 发明申请

US20090140440A1 MULTI-CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：多芯片堆叠结构及其制作方法
公开(公告)号：US20090140440A1
公开(公告)日：2009-06-04
申请号：US12266830
申请日：2008-11-07
申请人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
发明人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L25/50 , H01L21/56 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/858 , H01L2224/8592 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要翻译：提供了一种多芯片堆叠结构及其制造方法。制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上，通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。

2. 发明申请

US20080176358A1 Fabrication method of multichip stacking structure 审中-公开
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US20080176358A1
公开(公告)日：2008-07-24
申请号：US12009866
申请日：2008-01-23
申请人： Chung-Lun Liu , Chin-Huang Chang , Yi-Feng Chang , Jung-Pin Huang , Chih-Ming Huang
发明人： Chung-Lun Liu , Chin-Huang Chang , Yi-Feng Chang , Jung-Pin Huang , Chih-Ming Huang
IPC分类号： H01L21/56
CPC分类号： H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/4945 , H01L2224/73265 , H01L2224/83136 , H01L2224/83191 , H01L2224/838 , H01L2224/92247 , H01L2225/0651 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/07802 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention provides a fabrication method of a multi-chip stacking structure. The method includes steps of: stacking the first chips on the chip carrier in a step-like manner to form a first chip module; electrically connecting the first chip module to the chip carrier by a plurality of first bonding wires; stacking the second chips on the first chip module in step-like manner to form a second chip module, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer with the bottom chip deviated from the top chip horizontally in a direction toward the first bonding wires; and electrically connecting the bond pads of the second chip module to the chip carrier by a plurality of second bonding wires.
摘要翻译：本发明提供一种多芯片堆叠结构的制造方法。该方法包括以下步骤：以阶梯状方式堆叠芯片载体上的第一芯片以形成第一芯片模块; 通过多个第一接合线将第一芯片模块电连接到芯片载体; 在第一芯片模块上堆叠第二芯片以形成第二芯片模块，其中第二芯片模块的底部芯片通过粘合剂层堆叠在第一芯片模块的顶部芯片上，底部芯片偏离从顶部芯片沿着朝向第一接合线的方向水平地; 以及通过多个第二接合线将所述第二芯片模块的所述接合焊盘电连接到所述芯片载体。

3. 发明授权

US08896130B2 Multi-chip stack structure and method for fabricating the same 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US08896130B2
公开(公告)日：2014-11-25
申请号：US12266830
申请日：2008-11-07
申请人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
发明人： Chung-Lun Liu , Jung-Pin Huang , Yi-Feng Chang , Chin-Huang Chang
IPC分类号： H01L23/49 , H01L23/31 , H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC分类号： H01L25/50 , H01L21/56 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2224/858 , H01L2224/8592 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/15321 , H01L2924/15323 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.
摘要翻译：提供了一种多芯片堆叠结构及其制造方法。制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上，通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度并增加了布线粘合难度。

4. 发明申请

US20080174030A1 Multichip stacking structure 审中-公开
标题翻译：多芯片堆叠结构
公开(公告)号：US20080174030A1
公开(公告)日：2008-07-24
申请号：US12009865
申请日：2008-01-23
申请人： Chung-Lun Liu , Chin-Huang Chang , Yi-Feng Chang , Jung-Pin Huang , Chih-Ming Huang
发明人： Chung-Lun Liu , Chin-Huang Chang , Yi-Feng Chang , Jung-Pin Huang , Chih-Ming Huang
IPC分类号： H01L23/492
CPC分类号： H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/4945 , H01L2224/73265 , H01L2224/83136 , H01L2224/83191 , H01L2224/838 , H01L2224/92247 , H01L2225/0651 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/07802 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention provides a multi-chip stacking structure. The multichip stacking structure comprises: a chip carrier; a first and a second chip modules respectively having a plurality of first and a plurality of second chips, wherein each chips has a bond pad and the chips are stacked on the chip carrier in a step-like manner to expose the bond pads; and a plurality of bonding wires for electrically connecting the bond pads of the first and the second chip modules to the chip carrier, wherein a bottom chip of the second chip module is stacked on a top chip of the first chip module by an adhesive layer having fillers therein to support the bottom chip, and the bottom chip is deviated from the top chip horizontally in a direction toward the bonding wires of the first chip module.
摘要翻译：本发明提供一种多芯片堆叠结构。多芯片堆叠结构包括：芯片载体; 分别具有多个第一和多个第二芯片的第一和第二芯片模块，其中每个芯片具有接合焊盘，并且所述芯片以阶梯状方式堆叠在所述芯片载体上以暴露所述接合焊盘; 以及多个用于将第一和第二芯片模块的接合焊盘电连接到芯片载体的接合线，其中第二芯片模块的底部芯片通过粘合剂层被堆叠在第一芯片模块的顶部芯片上，该粘合层具有填充物以支撑底部芯片，并且底部芯片在朝向第一芯片模块的接合线的方向上水平地偏离顶部芯片。

5. 发明申请

US20060071220A1 Semiconductor package including light emitter and IC 有权
标题翻译：半导体封装包括发光器和IC
公开(公告)号：US20060071220A1
公开(公告)日：2006-04-06
申请号：US11237137
申请日：2005-09-28
申请人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
发明人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
IPC分类号： H01L31/12
CPC分类号： H01L25/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.
摘要翻译：公开了一种包括提供光的发光体的半导体封装，以指示半导体封装作为整体的状态和/或其中的芯片。根据半导体封装整体的状态和/或芯片，光发射器处于原始状态或闪烁状态或发光状态。除了发光体之外，半导体封装还包括载体和屏蔽结构。芯片和载体的至少一部分被屏蔽结构覆盖。光发射器可以被屏蔽结构部分地或完全地覆盖或密封。光发射器也可以部分地或完全暴露。屏蔽结构使得由其中密封的发光器提供的光可以通过其中以到达其外部，从而可以从外部识别半导体封装的整体状态和/或芯片半导体封装。

6. 发明授权

US07339199B2 Semiconductor package including light emitter and IC 有权
标题翻译：半导体封装包括发光器和IC
公开(公告)号：US07339199B2
公开(公告)日：2008-03-04
申请号：US11237137
申请日：2005-09-28
申请人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
发明人： Wei Lung Lu , Cheng Jen Liu , Chin-Huang Chang , Yi-Feng Chang
IPC分类号： H01L29/22
CPC分类号： H01L25/167 , H01L2224/48091 , H01L2224/48227 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012
摘要： The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.
摘要翻译：公开了一种包括提供光的发光体的半导体封装，以指示半导体封装作为整体的状态和/或其中的芯片。根据半导体封装整体的状态和/或芯片，光发射器处于原始状态或闪烁状态或发光状态。除了发光体之外，半导体封装还包括载体和屏蔽结构。芯片和载体的至少一部分被屏蔽结构覆盖。光发射器可以被屏蔽结构部分地或完全地覆盖或密封。光发射器也可以部分地或完全暴露。屏蔽结构使得由其中密封的发光器提供的光可以通过其中以到达其外部，从而可以从外部识别半导体封装的整体状态和/或芯片半导体封装。

7. 发明申请

US20130093038A1 Schottky Diode 有权
标题翻译：肖特基二极管
公开(公告)号：US20130093038A1
公开(公告)日：2013-04-18
申请号：US13271725
申请日：2011-10-12
申请人： Jam-Wem Lee , Yi-Feng Chang
发明人： Jam-Wem Lee , Yi-Feng Chang
IPC分类号： H01L29/861
CPC分类号： H01L29/872 , H01L29/0649 , H01L29/0692 , H01L29/161 , H01L29/20 , H01L29/66143
摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises a p-type region in a substrate; a first n-type well in the p-type region; a first p-type well in the p-type region; and a second p-type well in the first p-type well. A concentration of a p-type impurity in the first p-type well is less than a concentration of a p-type impurity in the second p-type well. Additional embodiments further comprise further n-type and p-type wells in the substrate. A method for forming a semiconductor structure is also disclosed.
摘要翻译：一个实施例是半导体结构。半导体结构包括在衬底中的p型区域; p型区域中的第一个n型阱; p型区域中的第一个p型阱; 和第一个p型井中的第二个p型井。第一p型阱中p型杂质的浓度小于第二p型阱中p型杂质的浓度。另外的实施例还包括在衬底中的另外的n型和p型阱。还公开了一种用于形成半导体结构的方法。

8. 发明申请

US20090085089A1 TWO-BIT FLASH MEMORY 有权
标题翻译：两位闪存
公开(公告)号：US20090085089A1
公开(公告)日：2009-04-02
申请号：US12099168
申请日：2008-04-08
申请人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
发明人： Ming-Cheng Chang , Wei-Ming Liao , Jer-Chyi Wang , Yi-Feng Chang
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L29/42336
摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.
摘要翻译：闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。突出部从基板的顶面延伸。控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。电介质层夹在控制栅极和两个浮栅之中。由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

9. 发明申请

US20130093010A1 High-Voltage Mosfets Having Current Diversion Region in Substrate Near Fieldplate 有权
标题翻译：高压滤波器在底板附近有电流导流区域
公开(公告)号：US20130093010A1
公开(公告)日：2013-04-18
申请号：US13271342
申请日：2011-10-12
申请人： Yun-Pei Huang , Yi-Feng Chang , Jam-Wem Lee
发明人： Yun-Pei Huang , Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/0653 , H01L29/063 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications.
摘要翻译：为了限制或防止电流拥挤，各种HV-MOSFET实施例包括设置在HV-MOSFET的漏极区附近并且在半导体衬底的上表面附近的电流分流区域。在一些实施例中，电流引流区域设置在HV-MOSFET的场板附近，其中场板还可以帮助减少或“平滑”漏极附近的电场，以帮助限制电流拥挤。在一些实施例中，电流分流区域是处于浮置电压电位的p掺杂，n掺杂或本征区域。该电流分流区可以将电流深度推入HV-MOSFET的衬底（相对于传统HV-MOSFET），从而减少ESD事件期间的电流拥挤。通过减少电流拥挤，电流分流区域使得本文公开的HV-MOSFET更加不可避免地存在ESD事件，因此在现实世界的应用中更可靠。

10. 发明申请

US20140061848A1 Schottky Isolated NMOS for Latch-Up Prevention 有权
标题翻译：肖特基隔离NMOS用于锁存预防
公开(公告)号：US20140061848A1
公开(公告)日：2014-03-06
申请号：US13603329
申请日：2012-09-04
申请人： Yi-Feng Chang , Jam-Wem Lee
发明人： Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L29/06 , H01L21/329
CPC分类号： H01L27/0921 , H01L21/823892 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.
摘要翻译：集成电路结构包括衬底，由衬底支撑的半导体器件以及围绕半导体器件设置的保护环结构，保护环结构形成肖特基结。在一个实施例中，肖特基结由p型金属接触和n型保护环形成。在一个实施例中，保护环结构电耦合到正或负电源电压。

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