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1. 发明申请

US20130297983A1 Data Processing System with Failure Recovery 有权
标题翻译：具有故障恢复的数据处理系统
公开(公告)号：US20130297983A1
公开(公告)日：2013-11-07
申请号：US13465214
申请日：2012-05-07
申请人： Chung-Li Wang , Lei Chen , Fan Zhang , Shaohua Yang , Johnson Yen
发明人： Chung-Li Wang , Lei Chen , Fan Zhang , Shaohua Yang , Johnson Yen
IPC分类号： G06F11/07 , H03M13/09 , G06F11/10 , H03M13/05
CPC分类号： H03M13/09 , G06F11/0727 , G06F11/0751 , G06F11/1076 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , H03M13/1111 , H03M13/1128 , H03M13/255 , H03M13/451 , H03M13/47
摘要： Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.
摘要翻译：本发明的各种实施例提供了具有故障恢复的数据处理系统的系统和方法。例如，公开了一种数据处理系统，其包括数据处理电路，可操作用于处理来自输入的数据块，并且基于数据块产生多个可能的结果;以及错误检测电路，用于测试多个可能的错误结果，并向数据处理电路报告多个可能的结果是否包含错误。数据处理系统可操作地输出误差检测电路没有发现错误的任何可能的结果。

2. 发明授权

US08775897B2 Data processing system with failure recovery 有权
标题翻译：数据处理系统故障恢复
公开(公告)号：US08775897B2
公开(公告)日：2014-07-08
申请号：US13465214
申请日：2012-05-07
申请人： Chung-Li Wang , Lei Chen , Fan Zhang , Shaohua Yang , Johnson Yen
发明人： Chung-Li Wang , Lei Chen , Fan Zhang , Shaohua Yang , Johnson Yen
IPC分类号： H03M13/00 , H03M13/09 , H03M13/47 , H03M13/25
CPC分类号： H03M13/09 , G06F11/0727 , G06F11/0751 , G06F11/1076 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , H03M13/1111 , H03M13/1128 , H03M13/255 , H03M13/451 , H03M13/47
摘要： Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.
摘要翻译：本发明的各种实施例提供了具有故障恢复的数据处理系统的系统和方法。例如，公开了一种数据处理系统，其包括数据处理电路，可操作用于处理来自输入的数据块，并且基于数据块产生多个可能的结果;以及错误检测电路，用于测试多个可能的错误结果，并向数据处理电路报告多个可能的结果是否包含错误。数据处理系统可操作地输出错误检测电路没有发现错误的任何可能的结果。

3. 发明申请

US20130275827A1 Multi-Section Non-Binary LDPC Decoder 审中-公开
标题翻译：多段非二进制LDPC解码器
公开(公告)号：US20130275827A1
公开(公告)日：2013-10-17
申请号：US13445834
申请日：2012-04-12
申请人： Chung-Li Wang , Lei Chen , Shaohua Yang , Zongwang Li , Herjen Wang , Ngok Ying Chu , Johnson Yen
发明人： Chung-Li Wang , Lei Chen , Shaohua Yang , Zongwang Li , Herjen Wang , Ngok Ying Chu , Johnson Yen
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1117 , G06F11/1076 , G11B20/1833 , G11B2020/185 , G11B2220/415 , H03M13/1171 , H03M13/658 , H03M13/6591 , H04L1/005 , H04L1/0057
摘要： Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages.
摘要翻译：本发明的各种实施例提供了用于解码多段非二进制LDPC解码器中码字的系统和方法。例如，公开了一种LDPC解码器，其包括可变节点处理器，其可操作以至少部分地基于对可变节点消息的校验节点执行变量节点更新，并且生成可变节点以检查节点消息;以及校验节点处理器，其可操作以处理所述变量节点在H矩阵的多个部分中的每一个上检查组中的节点消息，并将所述校验节点生成到可变节点消息。

4. 发明授权

US08947804B2 Systems and methods for combined binary and non-binary data processing 有权
标题翻译：用于组合二进制和非二进制数据处理的系统和方法
公开(公告)号：US08947804B2
公开(公告)日：2015-02-03
申请号：US13316758
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
发明人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
IPC分类号： G11B5/02 , H03M13/11
CPC分类号： G11B5/02 , H03M13/1171
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括组合数据解码器电路的数据处理系统。组合数据解码器电路包括：非二进制数据解码器电路和二进制数据解码器电路。

5. 发明申请

US20130148232A1 Systems and Methods for Combined Binary and Non-Binary Data Processing 有权
标题翻译：组合二进制和非二进制数据处理的系统和方法
公开(公告)号：US20130148232A1
公开(公告)日：2013-06-13
申请号：US13316758
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
发明人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
IPC分类号： G11B5/035 , H03M7/00
CPC分类号： G11B5/02 , H03M13/1171
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括组合数据解码器电路的数据处理系统。组合数据解码器电路包括：非二进制数据解码器电路和二进制数据解码器电路。

6. 发明授权

US08560930B2 Systems and methods for multi-level quasi-cyclic low density parity check codes 有权
标题翻译：多级准循环低密度奇偶校验码的系统和方法
公开(公告)号：US08560930B2
公开(公告)日：2013-10-15
申请号：US13316858
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
发明人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
IPC分类号： H03M13/03
CPC分类号： H03M13/036 , H03M13/1142 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.
摘要翻译：本发明的各种实施例提供了用于生成代码格式的系统和方法。所讨论的一种方法包括：本发明的各种实施例提供了用于生成代码格式的方法。这样的方法包括：接收具有陷阱集的低权重码字的指示; 选择基本矩阵的初始值; 通过初始值测试修改后的低权重码字以确定低权重码字的更新权重; 并通过初始值测试修改后的低权重码字，以确定捕获集是否保留。

7. 发明申请

US20120089888A1 Systems and Methods for Multi-Level Quasi-Cyclic Low Density Parity Check Codes 有权
标题翻译：多级准循环低密度奇偶校验码系统与方法
公开(公告)号：US20120089888A1
公开(公告)日：2012-04-12
申请号：US13316858
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
发明人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/036 , H03M13/1142 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.
摘要翻译：本发明的各种实施例提供了用于生成代码格式的系统和方法。所讨论的一种方法包括：本发明的各种实施例提供了用于生成代码格式的方法。这样的方法包括：接收具有陷阱集的低权重码字的指示; 选择基本矩阵的初始值; 通过初始值测试修改后的低权重码字以确定低权重码字的更新权重; 并通过初始值测试修改后的低权重码字，以确定捕获集是否保留。

8. 发明授权

US08756478B2 Multi-level LDPC layer decoder 有权
标题翻译：多级LDPC层解码器
公开(公告)号：US08756478B2
公开(公告)日：2014-06-17
申请号：US13300078
申请日：2011-11-18
申请人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
发明人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
IPC分类号： H03M13/00
CPC分类号： H03M13/1117 , G06F11/1076 , H03M13/1122 , H03M13/1125 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/6577 , H03M13/658 , H03M13/6591
摘要： Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding.
摘要翻译：本发明的各种实施例涉及用于解码数据的方法和装置，更具体地涉及用于多级分层LDPC解码的方法和装置。例如，在一个实施例中，装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。校验节点处理器包括可用于识别可变节点中的最小值，下一个最小值和最小值的索引以检查节点消息的最小取景器电路。可变节点处理器和校验节点处理器可操作以执行分层多级解码。

9. 发明申请

US20130061107A1 Multi-Level LDPC Layer Decoder 有权
标题翻译：多级LDPC层解码器
公开(公告)号：US20130061107A1
公开(公告)日：2013-03-07
申请号：US13300078
申请日：2011-11-18
申请人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
发明人： Chung-Li Wang , Zongwang Li , Lei Chen , Johnson Yen
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1117 , G06F11/1076 , H03M13/1122 , H03M13/1125 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/6577 , H03M13/658 , H03M13/6591
摘要： Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding.
摘要翻译：本发明的各种实施例涉及用于解码数据的方法和装置，更具体地涉及用于多级分层LDPC解码的方法和装置。例如，在一个实施例中，装置包括可变节点处理器和校验节点处理器。可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。校验节点处理器包括可用于识别可变节点中的最小值，下一个最小值和最小值的索引以检查节点消息的最小取景器电路。可变节点处理器和校验节点处理器可操作以执行分层多级解码。

10. 发明申请

US20130111289A1 SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING 有权
标题翻译：双过程数据解码的系统和方法
公开(公告)号：US20130111289A1
公开(公告)日：2013-05-02
申请号：US13284730
申请日：2011-10-28
申请人： Fan Zhang , Lei Chen , Zongwang Li , Shaohua Yang , Yang Han , Wu Chang
发明人： Fan Zhang , Lei Chen , Zongwang Li , Shaohua Yang , Yang Han , Wu Chang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1108 , G11B20/1833 , G11B2020/185 , H03M13/1111 , H03M13/1128 , H03M13/1142 , H03M13/1171 , H03M13/3707 , H03M13/451
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system. The data decoding system includes a data decoder circuit and a simplified maximum likelihood value modification circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output. The simplified maximum likelihood value modification circuit is operable to identify a symbol of the first decoded output associated with the point of failure, and to modify a subset of values associated with the identified symbol to yield a modified decoded output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括数据解码系统的数据处理系统。数据解码系统包括数据解码器电路和简化的最大似然值修正电路。数据解码器电路可操作以将数据解码算法应用于解码器输入，以产生第一解码输出和第一解码输出的至少一个故障点的指示。简化的最大似然值修改电路可操作以识别与故障点相关联的第一解码输出的符号，并且修改与所识别的符号相关联的值的子集以产生经修改的解码输出。

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