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1. 发明申请

US20050085055A1 End of range (EOR) secondary defect engineering using substitutional carbon doping 有权
标题翻译：使用替代碳掺杂的范围终点（EOR）二次缺陷工程
公开(公告)号：US20050085055A1
公开(公告)日：2005-04-21
申请号：US10688047
申请日：2003-10-17
申请人： Chung Tan , Jinping Liu , Hyeok Lee , Bangun Indajang , Eng Chor , Shiang Ong
发明人： Chung Tan , Jinping Liu , Hyeok Lee , Bangun Indajang , Eng Chor , Shiang Ong
IPC分类号： C30B1/00 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/74 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02447 , H01L21/02532 , H01L21/26506 , H01L21/26513 , H01L21/74 , H01L29/6659
摘要： A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.
摘要翻译：实现了在光栅掺杂分布的间隙a-c硅界面处将碳结合到晶片中的方法。提供体硅衬底。在体硅衬底上沉积碳掺杂硅层。生长外延硅层覆盖碳掺杂硅层以提供集成电路器件制造的起始晶片。通过以下步骤在起始晶片上制造集成电路器件。在起始晶片上形成栅电极。将LDD和源极和漏极区域注入到与栅电极相邻的起始晶片中。植入铟以形成与LDD区域相邻并且位于栅电极下方的卤素植入物，其中所述卤素注入延伸到外延硅层和碳掺杂硅层之间的界面，其中碳掺杂硅层中的碳离子用作用于由光晕植入物形成的硅间隙的硅间隙槽，以防止范围二次缺陷形成的结束。

2. 发明申请

US20050136623A1 Shallow amorphizing implant for gettering of deep secondary end of range defects 失效
标题翻译：浅非晶化植入物用于吸收深度范围缺陷的二次端
公开(公告)号：US20050136623A1
公开(公告)日：2005-06-23
申请号：US10743247
申请日：2003-12-22
申请人： Chung Tan , Hyeokjae Lee , Eng Chor , Elgin Quek
发明人： Chung Tan , Hyeokjae Lee , Eng Chor , Elgin Quek
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L21/322
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
摘要翻译：口袋植入法减少缺陷。我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。非晶浅植入区域形成在无定形袋区域上方的第二深度处。非晶浅植入区域之上的衬底优选保持结晶。我们执行S / D植入程序以形成深S / D区域。我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。

3. 发明申请

US20070117326A1 MATERIAL ARCHITECTURE FOR THE FABRICATION OF LOW TEMPERATURE TRANSISTOR 审中-公开
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20070117326A1
公开(公告)日：2007-05-24
申请号：US11625789
申请日：2007-01-22
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083 , H01L29/6659
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

4. 发明申请

US20060006427A1 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20060006427A1
公开(公告)日：2006-01-12
申请号：US10886442
申请日：2004-07-07
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

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