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1. 发明申请

US20050029566A1 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 有权
标题翻译：使用焊盘保护层在铜CMOS电路中制造新的金属 - 绝缘体 - 金属（MIM）电容器结构的方法
公开(公告)号：US20050029566A1
公开(公告)日：2005-02-10
申请号：US10935376
申请日：2004-09-07
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/08 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。该方法提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

2. 发明授权

US06812088B1 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 失效
标题翻译：使用焊盘保护层在铜CMOS电路中制造新的金属 - 绝缘体 - 金属（MIM）电容器结构的方法
公开(公告)号：US06812088B1
公开(公告)日：2004-11-02
申请号：US10167856
申请日：2002-06-11
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： This MIM structure provides metal capacitors with high figure of merit Q (Xc/R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：该MIM结构提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺同时形成焊盘触点和铜互连水平。在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。金属保护缓冲器保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

3. 发明授权

US06881996B2 Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 有权
标题翻译：金属绝缘体金属（MIM）电容器结构在铜CMOS电路中使用焊盘保护层
公开(公告)号：US06881996B2
公开(公告)日：2005-04-19
申请号：US10935376
申请日：2004-09-07
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/08 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。该方法提供具有高品质因数Q（X / C / R）的金属电容器，并且不需要额外的掩模和金属层。该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。在铜上形成绝缘（Si 3 N 4 N 4）金属保护层，形成电容器电极间电介质层。使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

4. 发明授权

US06472721B2 Dual damascene interconnect structures that include radio frequency capacitors and inductors 有权
标题翻译：双镶嵌互连结构，包括射频电容器和电感器
公开(公告)号：US06472721B2
公开(公告)日：2002-10-29
申请号：US09963749
申请日：2001-09-27
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L2943
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

5. 发明授权

US06329234B1 Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow 有权
标题翻译：铜工艺兼容CMOS金属 - 绝缘体 - 金属电容器结构及其工艺流程
公开(公告)号：US06329234B1
公开(公告)日：2001-12-11
申请号：US09624026
申请日：2000-07-24
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

6. 发明授权

US06667217B1 Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process 有权
标题翻译：使用亚0.18μmCMOS工艺制造镶嵌铜电感器结构的方法
公开(公告)号：US06667217B1
公开(公告)日：2003-12-23
申请号：US09795115
申请日：2001-03-01
申请人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
发明人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/042 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.
摘要翻译：已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构，以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。

7. 发明申请

US20120223796A1 VARIABLE INDUCTOR 审中-公开
标题翻译：可变电感器
公开(公告)号：US20120223796A1
公开(公告)日：2012-09-06
申请号：US13372503
申请日：2012-02-14
申请人： Kai-Yi Huang , Yuh-Sheng Jean , Ta-Hsun Yeh
发明人： Kai-Yi Huang , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01F29/02
CPC分类号： H01F21/12 , H01F2021/125 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： A variable inductor includes an inductor element and a first inductance adjusting circuit. The first inductance adjusting circuit includes a first open-loop structure and a first switch element. The first switch element is coupled to the first open-loop structure. When the first switch element is in a conducting state, the first open-loop structure and the first switch element forms a first closed-loop to induce a first magnetic flux which alters a magnetic flux from the inductor element in operation.
摘要翻译：可变电感器包括电感器元件和第一电感调节电路。第一电感调节电路包括第一开环结构和第一开关元件。第一开关元件耦合到第一开环结构。当第一开关元件处于导通状态时，第一开环结构和第一开关元件形成第一闭环以产生在操作中改变来自电感器元件的磁通量的第一磁通量。

8. 发明授权

US07936245B2 Stacked structure of a spiral inductor 有权
标题翻译：螺旋电感器的堆叠结构
公开(公告)号：US07936245B2
公开(公告)日：2011-05-03
申请号：US12773024
申请日：2010-05-04
申请人： Kai-Yi Huang , Yuh-Sheng Jean , Ta-Hsun Yeh
发明人： Kai-Yi Huang , Yuh-Sheng Jean , Ta-Hsun Yeh
IPC分类号： H01F5/00
CPC分类号： H01F17/0006
摘要： A stacked structure of a spiral inductor includes a first metal layer, a second metal layer, a first set of vias, and a second set of vias. The first metal layer includes a first segment, a second segment, and a third segment, wherein the layout direction of the third segment is different from the layout direction of the first and second segments. The second metal layer includes a fourth segment, a fifth segment, and a sixth segment connected to the fifth segment, wherein the layout direction of the sixth segment is different from the layout direction of the fourth and fifth segments. The first set of vias connects the first and fourth segments, and they construct a first shunt winding. The second set of vias connects the second and fifth segments, and they construct a second shunt winding. The third and sixth segments construct a crossover region.
摘要翻译：螺旋电感器的堆叠结构包括第一金属层，第二金属层，第一组通孔和第二组通孔。第一金属层包括第一段，第二段和第三段，其中第三段的布局方向与第一段和第二段的布局方向不同。第二金属层包括第四段，第五段和连接到第五段的第六段，其中第六段的布局方向与第四段和第五段的布局方向不同。第一组通孔连接第一和第四段，并构成第一个分流绕组。第二组通孔连接第二和第五段，并且它们构成第二分流绕组。第三和第六段构成交叉区域。

9. 发明授权

US07612645B2 Integrated inductor 有权
标题翻译：集成电感
公开(公告)号：US07612645B2
公开(公告)日：2009-11-03
申请号：US11548687
申请日：2006-10-11
申请人： Ta-Hsun Yeh , Yuh-Sheng Jean
发明人： Ta-Hsun Yeh , Yuh-Sheng Jean
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/34 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated inductor formed on a substrate comprises a metal layer pattern, a via layer pattern overlapping and electrically connected to the metal layer, and a redistribution layer pattern overlapping and electrically connected to the via layer. The metal layer pattern, the via layer pattern, and the redistribution layer pattern are a coil pattern.
摘要翻译：形成在基板上的集成电感器包括金属层图案，与金属层重叠并电连接的通孔层图案，以及重叠并电连接到通孔层的再分布层图案。金属层图案，通孔层图案和再分布层图案是线圈图案。

10. 发明申请

US20080251841A1 MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US20080251841A1
公开(公告)日：2008-10-16
申请号：US12056293
申请日：2008-03-27
申请人： Kai-Yi Huang , Ta-Hsun Yeh , Yuh-Sheng Jean
发明人： Kai-Yi Huang , Ta-Hsun Yeh , Yuh-Sheng Jean
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66659
摘要： The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required.
摘要翻译：在本发明中提供的MOS晶体管的结构具有从源极，漏极或衬底中的两个区域去除的LDD（轻掺杂漏极）和卤素掺杂区域，用于当作为压控电阻器工作时提高线性范围。通过简单地使用没有额外掩模的逻辑运算层来修改MOS工艺的标准掩模来执行LDD和光晕掺杂区的去除。

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