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1. 发明授权

US06329234B1 Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow 有权
标题翻译：铜工艺兼容CMOS金属 - 绝缘体 - 金属电容器结构及其工艺流程
公开(公告)号：US06329234B1
公开(公告)日：2001-12-11
申请号：US09624026
申请日：2000-07-24
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

2. 发明授权

US06881996B2 Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 有权
标题翻译：金属绝缘体金属（MIM）电容器结构在铜CMOS电路中使用焊盘保护层
公开(公告)号：US06881996B2
公开(公告)日：2005-04-19
申请号：US10935376
申请日：2004-09-07
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/08 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。该方法提供具有高品质因数Q（X / C / R）的金属电容器，并且不需要额外的掩模和金属层。该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。在铜上形成绝缘（Si 3 N 4 N 4）金属保护层，形成电容器电极间电介质层。使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

3. 发明授权

US06472721B2 Dual damascene interconnect structures that include radio frequency capacitors and inductors 有权
标题翻译：双镶嵌互连结构，包括射频电容器和电感器
公开(公告)号：US06472721B2
公开(公告)日：2002-10-29
申请号：US09963749
申请日：2001-09-27
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L2943
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

4. 发明申请

US20050029566A1 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 有权
标题翻译：使用焊盘保护层在铜CMOS电路中制造新的金属 - 绝缘体 - 金属（MIM）电容器结构的方法
公开(公告)号：US20050029566A1
公开(公告)日：2005-02-10
申请号：US10935376
申请日：2004-09-07
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/08 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。该方法提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

5. 发明授权

US06812088B1 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 失效
标题翻译：使用焊盘保护层在铜CMOS电路中制造新的金属 - 绝缘体 - 金属（MIM）电容器结构的方法
公开(公告)号：US06812088B1
公开(公告)日：2004-11-02
申请号：US10167856
申请日：2002-06-11
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： This MIM structure provides metal capacitors with high figure of merit Q (Xc/R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：该MIM结构提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺同时形成焊盘触点和铜互连水平。在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。金属保护缓冲器保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

6. 发明授权

US06667217B1 Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process 有权
标题翻译：使用亚0.18μmCMOS工艺制造镶嵌铜电感器结构的方法
公开(公告)号：US06667217B1
公开(公告)日：2003-12-23
申请号：US09795115
申请日：2001-03-01
申请人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
发明人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/042 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.
摘要翻译：已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构，以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。

7. 发明授权

US5950087A Method to make self-aligned source etching available in split-gate flash 有权
标题翻译：在分流栅闪光中进行自对准源蚀刻的方法
公开(公告)号：US5950087A
公开(公告)日：1999-09-07
申请号：US151154
申请日：1998-09-10
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Jaung-Ke Yeh , Kuo-Reay Peng , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Jaung-Ke Yeh , Kuo-Reay Peng , Di-Son Kuo
IPC分类号： H01L21/336 , H01L21/8247 , H01L29/423
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825
摘要： A method is provided for forming a common self-aligned source line in order to reduce the number of surface contacts and at the same time alleviate the field oxide encroachment into the cell area. Thus, the size of the split-gate flash memory is substantially reduced on both accounts. This is accomplished by forming a buffer polysilicon layer over the floating gate to serve as an etch stop to protect the first poly-oxide of the floating gate during the self-aligned source etching.
摘要翻译：提供了一种用于形成公共自对准源极线以便减少表面接触的数量并同时减轻场氧化物侵入电池区域的方法。因此，两个帐户都显着减少了分闸门闪存的大小。这通过在浮置栅极上形成缓冲多晶硅层来实现，以在自对准源蚀刻期间用作蚀刻停止层以保护浮置栅极的第一多晶氧化物。

8. 发明授权

US5903499A Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase 失效
标题翻译：使用负栅极源擦除后跟高负栅极擦除擦除闪存EEPROM的方法
公开(公告)号：US5903499A
公开(公告)日：1999-05-11
申请号：US928227
申请日：1997-09-12
申请人： Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
发明人： Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.
摘要翻译：一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除快闪EEPROM单元的方法是首先向EEPROM单元的源极施加适度高的正电压脉冲。同时，向控制栅极施加第一相对较大的负电压。同时对半导体衬底施加接地参考电位。在同一时间，排水沟漂浮。然后通过漂浮源极和漏极并将接地参考电位施加到半导体衬底来去除快闪EEPROM单元。同时，向控制栅极施加第二相对大的负电压脉冲。

9. 发明授权

US5838618A Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure 失效
标题翻译：用于消除循环感应闪速EEPROM单元写入/擦除阈值闭合的双模式擦除方法
公开(公告)号：US5838618A
公开(公告)日：1998-11-17
申请号：US927472
申请日：1997-09-11
申请人： Jian-Hsing Lee , Juang-Ker Yeh , Kuo-Reay Peng , Ming-Chou Ho
发明人： Jian-Hsing Lee , Juang-Ker Yeh , Kuo-Reay Peng , Ming-Chou Ho
IPC分类号： G11C16/14 , G11C16/04 , G11C7/00
CPC分类号： G11C16/14
摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.
摘要翻译：一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。

10. 发明授权

US06661060B2 Low capacitance ESD protection device 有权
公开(公告)号：US06661060B2
公开(公告)日：2003-12-09
申请号：US10213613
申请日：2002-08-07
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Shih-Chyi Wong
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Shih-Chyi Wong
IPC分类号： H01L2362
CPC分类号： H01L27/0251 , H01L27/0727
摘要： An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N+ diffusion) next to the it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion) is located on either side of each source (N+ diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P+ diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

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