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1. 发明申请

US20110305062A1 MEMORY CELL AND MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：使用该存储单元的存储单元和存储器件
公开(公告)号：US20110305062A1
公开(公告)日：2011-12-15
申请号：US12887316
申请日：2010-09-21
申请人： Chun Won BYUN , Byeong Hoon Kim , Sung Min Yoon , Kyoung Ik Cho , Sang Hee Park , Chi Sun Hwang , Min Ki Ryu , Shin Hyuk Yang , Oh Sang Kwon , Eun Suk Park
发明人： Chun Won BYUN , Byeong Hoon Kim , Sung Min Yoon , Kyoung Ik Cho , Sang Hee Park , Chi Sun Hwang , Min Ki Ryu , Shin Hyuk Yang , Oh Sang Kwon , Eun Suk Park
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations.
摘要翻译：提供了一种存储器单元和使用该存储单元的存储器件，特别地，包括作为存储单元的铁电晶体管的非易失性非破坏性可读随机存取存储单元和使用该存储单元的存储器件。存储单元包括具有施加了参考电压的漏极的铁电晶体管，被配置为允许铁电晶体管的源被响应于扫描信号连接到第一线的第一开关，以及被配置为允许铁电晶体管的栅极响应于扫描信号连接到第二线。存储器件允许随机访问并执行非破坏性读出（NDRO）操作。

2. 发明申请

US20100006837A1 COMPOSITION FOR OXIDE SEMICONDUCTOR THIN FILM, FIELD EFFECT TRANSISTOR USING THE COMPOSITION AND METHOD OF FABRICATING THE TRANSISTOR 审中-公开
标题翻译：用于氧化物半导体薄膜的组合物，使用该组合物的场效应晶体管和制造晶体管的方法
公开(公告)号：US20100006837A1
公开(公告)日：2010-01-14
申请号：US12496558
申请日：2009-07-01
申请人： Doo Hee Cho , Sang Hee Park , Chi Sun Hwang , Hye Yong Chu , Kyoung Ik Cho , Shin Hyuk Yang , Chun Won Byun , Eun Suk Park , Oh Sang Kwon , Min Ki Ryu , Jae Heon Shin , Woo Seok Cheong , Sung Mook Chung , Jeong Ik Lee
发明人： Doo Hee Cho , Sang Hee Park , Chi Sun Hwang , Hye Yong Chu , Kyoung Ik Cho , Shin Hyuk Yang , Chun Won Byun , Eun Suk Park , Oh Sang Kwon , Min Ki Ryu , Jae Heon Shin , Woo Seok Cheong , Sung Mook Chung , Jeong Ik Lee
IPC分类号： H01L29/786 , H01L21/336 , H01B1/08
CPC分类号： H01L29/7869 , C23C14/08 , H01L29/247
摘要： Provided are a composition for an oxide semiconductor thin film, a field effect transistor using the same and a method of fabricating the field effect transistor. The composition includes an aluminum oxide, a zinc oxide, an indium oxide and a tin oxide. The thin film formed of the composition is in amorphous phase. The field effect transistor having an active layer formed of the composition can have an improved electrical characteristic and be fabricated by a low temperature process.
摘要翻译：提供了一种用于氧化物半导体薄膜的组合物，使用该组合物的场效应晶体管和制造场效应晶体管的方法。该组合物包括氧化铝，氧化锌，氧化铟和氧化锡。由组合物形成的薄膜是非晶相。具有由组合物形成的有源层的场效应晶体管可以具有改进的电特性并通过低温工艺制造。

3. 发明授权

US08558295B2 Nonvolatile memory cell and method of manufacturing the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US08558295B2
公开(公告)日：2013-10-15
申请号：US12838878
申请日：2010-07-19
申请人： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
发明人： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
IPC分类号： H01G7/06
CPC分类号： H01L29/6684 , B82Y10/00 , G11C11/22 , H01L21/28291 , H01L27/1159 , H01L29/78391
摘要： Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.
摘要翻译：提供一种非易失性存储单元及其制造方法。非易失性存储单元包括存储晶体管和驱动晶体管。存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。存储晶体管和驱动晶体管设置在同一衬底上。非易失性存储单元在可见光区域是透明的。

4. 发明申请

US20110266542A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110266542A1
公开(公告)日：2011-11-03
申请号：US13094933
申请日：2011-04-27
申请人： Min Ki RYU , Sang Hee Park , Chi Sun Hwang , Kyoung Ik Cho
发明人： Min Ki RYU , Sang Hee Park , Chi Sun Hwang , Kyoung Ik Cho
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L27/124 , H01L27/1225 , H01L29/78648
摘要： Provided are a semiconductor device including a dual gate transistor and a method of fabricating the same. The semiconductor device includes a lower gate electrode, an upper gate electrode on the lower gate electrode, a contact plug interposed between the lower gate electrode and the upper gate electrode, and connecting the lower gate electrode to the upper gate electrode, and a functional electrode spaced apart from the upper gate electrode and formed at the same height as the upper gate electrode. The dual gate transistor exhibiting high field effect mobility is applied to the semiconductor device, so that characteristics of the semiconductor device can be improved. In particular, since no additional mask or deposition process is necessary, a large-area high-definition semiconductor device can be mass-produced with neither an increase in process cost nor a decrease in yield.
摘要翻译：提供一种包括双栅晶体管的半导体器件及其制造方法。半导体器件包括下栅极电极，下栅电极上的上栅电极，插入在下栅电极和上栅电极之间的接触插塞，并将下栅电极连接到上栅电极，功能电极与上栅电极间隔开并形成与上栅电极相同的高度。表现出高场效应迁移率的双栅极晶体管被施加到半导体器件，从而可以提高半导体器件的特性。特别是，由于不需要附加的掩模或沉积工艺，所以大面积的高分辨率半导体器件既可以增加工艺成本也不会降低产量。

5. 发明申请

US20120242370A1 INVERTER, NAND GATE, AND NOR GATE 失效
标题翻译：逆变器，NAND门和NOR门
公开(公告)号：US20120242370A1
公开(公告)日：2012-09-27
申请号：US13355479
申请日：2012-01-20
申请人： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
发明人： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
IPC分类号： H03K19/094
CPC分类号： H03K3/012 , H03K19/094 , H03K19/20
摘要： Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
摘要翻译：公开了一种逆变器，NAND门和NOR门。逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。

6. 发明授权

US08570066B2 Inverter, NAND gate, and NOR gate 失效
公开(公告)号：US08570066B2
公开(公告)日：2013-10-29
申请号：US13355479
申请日：2012-01-20
申请人： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
发明人： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K3/012 , H03K19/094 , H03K19/20
摘要： Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

7. 发明授权

US09053937B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09053937B2
公开(公告)日：2015-06-09
申请号：US13087363
申请日：2011-04-14
申请人： Sang Hee Park , Chi Sun Hwang , Chun Won Byun , Elvira M. C. Fortunato , Rodrigo F. P. Martins , Ana R. X. Barros , Nuno F. O. Correia , Pedro M. C. Barquinha , Vitor M. L. Figueiredo
发明人： Sang Hee Park , Chi Sun Hwang , Chun Won Byun , Elvira M. C. Fortunato , Rodrigo F. P. Martins , Ana R. X. Barros , Nuno F. O. Correia , Pedro M. C. Barquinha , Vitor M. L. Figueiredo
IPC分类号： H01L29/22 , H01L21/02 , C23C14/08 , H01L27/12 , H01L29/49 , H01L29/786 , H01L29/94 , H01L29/66 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/02565 , C23C14/08 , C23C14/086 , C23C14/087 , H01L21/02422 , H01L21/02579 , H01L21/02617 , H01L21/02628 , H01L21/02631 , H01L21/823857 , H01L27/092 , H01L27/1203 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/94
摘要： Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.
摘要翻译：提供一种使用p型氧化物半导体层的半导体器件及其制造方法。该装置包括由至少一种氧化物形成的p型氧化物层，所述氧化物选自由含铜（Cu）的一氧化碳，含锡（Sn）的一氧化锡，含有Cu-Sn的铜锡氧化物合金和含有Ni-Sn合金的镍锡氧化物。因此，使用p型氧化物层容易显影透明或不透明的装置。由于使用低温工艺形成的氧化物层被应用于半导体器件，所以可以简化半导体器件的制造工艺，并且可以降低制造成本。

8. 发明申请

US20110253997A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110253997A1
公开(公告)日：2011-10-20
申请号：US13087363
申请日：2011-04-14
申请人： Sang Hee Park , Chi Sun Hwang , Chun Won Byun , Elvira M.C. Fortunato , Rodrigo F.P. Martins , Ana R.X. Barros , Nuno F.O. Correia , Pedro M.C. Barquinha , Vitor M.L. Figueiredo
发明人： Sang Hee Park , Chi Sun Hwang , Chun Won Byun , Elvira M.C. Fortunato , Rodrigo F.P. Martins , Ana R.X. Barros , Nuno F.O. Correia , Pedro M.C. Barquinha , Vitor M.L. Figueiredo
IPC分类号： H01L29/22 , H01L21/36
CPC分类号： H01L21/02565 , C23C14/08 , C23C14/086 , C23C14/087 , H01L21/02422 , H01L21/02579 , H01L21/02617 , H01L21/02628 , H01L21/02631 , H01L21/823857 , H01L27/092 , H01L27/1203 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/94
摘要： Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.
摘要翻译：提供一种使用p型氧化物半导体层的半导体器件及其制造方法。该装置包括由至少一种氧化物形成的p型氧化物层，所述氧化物选自由含铜（Cu）的一氧化碳，含锡（Sn）的一氧化锡，含有Cu-Sn的铜锡氧化物合金和含有Ni-Sn合金的镍锡氧化物。因此，使用p型氧化物层容易显影透明或不透明的装置。由于使用低温工艺形成的氧化物层被应用于半导体器件，所以可以简化半导体器件的制造工艺，并且可以降低制造成本。

9. 发明申请

US20120286271A1 OXIDE THIN FILM TRANSISTOR RESISTANT TO LIGHT AND BIAS STRESS, AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：氧化物薄膜晶体管耐光和偏应力及其制造方法
公开(公告)号：US20120286271A1
公开(公告)日：2012-11-15
申请号：US13467674
申请日：2012-05-09
申请人： Him Chan OH , Sang Hee Park , Chi Sun Hwang , Min Ki Ryu
发明人： Him Chan OH , Sang Hee Park , Chi Sun Hwang , Min Ki Ryu
IPC分类号： H01L29/786 , H01L29/04 , H01L21/336 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/7869
摘要： Disclosed are an oxide thin film transistor resistant to light and bias stress, and a method of manufacturing the same. The method includes forming a gate electrode on a substrate; forming a gate insulating layer on an upper part including the gate electrode; forming a source electrode and a drain electrode on the insulating layer; forming an active layer insulated from the gate electrode by the gate insulating layer and formed of an oxide semiconductor and a diffusion barrier film; and forming a protective layer on a portion of the source electrode and drain electrode and the upper part including the active layer, wherein the diffusion barrier film reduces movement of holes and prevents ionized oxygen vacancies from being diffused.
摘要翻译：公开了耐光和偏压应力的氧化物薄膜晶体管及其制造方法。该方法包括在基板上形成栅电极; 在包括所述栅电极的上部形成栅极绝缘层; 在绝缘层上形成源电极和漏电极; 通过所述栅极绝缘层形成与所述栅极绝缘的有源层，并由氧化物半导体和扩散阻挡膜形成; 以及在源电极和漏电极以及包括有源层的上部的一部分上形成保护层，其中扩散阻挡膜减小空穴的移动并防止电离的氧空位扩散。

10. 发明授权

US07875559B2 Method of manufacturing P-type ZnO semiconductor layer using atomic layer deposition and thin film transistor including the P-type ZnO semiconductor layer 有权
标题翻译：使用原子层沉积制造P型ZnO半导体层的方法和包括P型ZnO半导体层的薄膜晶体管
公开(公告)号：US07875559B2
公开(公告)日：2011-01-25
申请号：US11970836
申请日：2008-01-08
申请人： Sang Hee Park , Chi Sun Hwang , Hye Yong Chu , Jeong Ik Lee
发明人： Sang Hee Park , Chi Sun Hwang , Hye Yong Chu , Jeong Ik Lee
IPC分类号： H01L21/00 , H01L21/469 , H01L21/31
CPC分类号： H01L29/7869 , C23C16/308 , C23C16/34 , C23C16/407 , C23C16/45529 , C30B25/02 , C30B29/16 , H01L21/02554 , H01L21/02579 , H01L21/0262
摘要： Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.
摘要翻译：提供了使用包含构成薄层的元素的前体和包含p型ZnO半导体层的薄膜晶体管（TFT）之间的表面化学反应来制造透明N掺杂p型ZnO半导体层的方法。该方法包括以下步骤：准备衬底并将衬底装载到腔室中; 将Zn前体和氧前体注入到室中，并且使用原子层沉积（ALD）技术在Zn前体和氧前体之间引起表面化学反应，以在衬底上形成ZnO薄层; 并将Zn前体和氮前体注入到室中，并且使Zn前体和氮前体之间的表面化学反应在ZnO薄层上形成掺杂层。

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