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1. 发明申请

US20080044668A1 ULTRALOW DIELECTRIC CONSTANT LAYER WITH CONTROLLED BIAXIAL STRESS 有权
标题翻译：超导介质恒定层与受控双向应力
公开(公告)号：US20080044668A1
公开(公告)日：2008-02-21
申请号：US11034479
申请日：2005-01-13
申请人： Christos Dimitrakopoulos , Stephen Gates , Alfred Grill , Michael Lane , Eric Liniger , Xiao Liu , Son Nguyen , Deborah Neumayer , Thomas Shaw
发明人： Christos Dimitrakopoulos , Stephen Gates , Alfred Grill , Michael Lane , Eric Liniger , Xiao Liu , Son Nguyen , Deborah Neumayer , Thomas Shaw
IPC分类号： B32B9/04 , B32B13/04
CPC分类号： H01L21/76834 , C23C16/30 , C23C16/56 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02348 , H01L21/3105 , H01L21/31058 , H01L21/31633 , H01L21/76801 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , Y10T428/249953 , Y10T428/249969 , Y10T428/249979
摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.
摘要翻译：描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜的氧和水各自小于10ppm。还通过使用介电常数不大于2.8的方法描述材料。本发明克服了低双轴应力低于46MPa的薄膜形成问题。

2. 发明申请

US20060165891A1 SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same 失效
标题翻译： SiCOH介电材料具有改善的韧性和改善的Si-C键合，含有其的半导体器件及其制造方法
公开(公告)号：US20060165891A1
公开(公告)日：2006-07-27
申请号：US11132108
申请日：2005-05-18
申请人： Daniel Edelstein , Stephen Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert Miller , Deborah Neumayer , Son Nguyen
发明人： Daniel Edelstein , Stephen Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert Miller , Deborah Neumayer , Son Nguyen
IPC分类号： C23C16/00 , B05D3/00
CPC分类号： H01L31/103 , Y10T428/31663
摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C≡CH2, C≡C or a [S]n linkage, where n is a defined above.
摘要翻译：提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k介电材料，其包括Si，C，O和H的原子，其中C原子的一部分键合为Si-CH _{3个官能团，另外一部分C原子键合为Si-R-Si，其中R是苯基， - [CH 2 N] - 其中n大于或等于1，HC-CH，C≡CH2，C≡C或[S] n N连接，其中n是定义的以上。}

3. 发明申请

US20050194619A1 SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same 有权
标题翻译： SiCOH介电材料具有改善的韧性和改善的Si-C键合，含有其的半导体器件及其制造方法
公开(公告)号：US20050194619A1
公开(公告)日：2005-09-08
申请号：US11040778
申请日：2005-01-21
申请人： Daniel Edelstein , Stephen Gates , Alfred Grill , Michael Lane , Robert Miller , Deborah Neumayer , Son Nguyen
发明人： Daniel Edelstein , Stephen Gates , Alfred Grill , Michael Lane , Robert Miller , Deborah Neumayer , Son Nguyen
IPC分类号： H01L27/148 , H01L31/103
CPC分类号： H01L31/103 , Y10T428/31663
摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C═C or a [S]n linkage, where n is a defined above.
摘要翻译：提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k介电材料，其包括Si，C，O和H的原子，其中C原子的一部分键合为Si-CH _{3个官能团，另外一部分C原子键合为Si-R-Si，其中R是苯基， - [CH 2 N] - 其中n大于或等于1，HC-CH，C-CH 2，CC或[S] N n连接，其中n定义如上。}

4. 发明申请

US20080118717A1 HARDMASK FOR IMPROVED RELIABILITY OF SILICON BASED DIELECTRICS 审中-公开
公开(公告)号：US20080118717A1
公开(公告)日：2008-05-22
申请号：US12018640
申请日：2008-01-23
申请人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
发明人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
IPC分类号： B32B3/00
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/3122 , H01L21/76807 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10T428/24802 , H01L2924/00
摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

5. 发明申请

US20060091559A1 Hardmask for improved reliability of silicon based dielectrics 有权
公开(公告)号：US20060091559A1
公开(公告)日：2006-05-04
申请号：US10981233
申请日：2004-11-04
申请人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
发明人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
IPC分类号： H01L21/4763 , H01L23/52 , H01L21/31
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/3122 , H01L21/76807 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10T428/24802 , H01L2924/00
摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

6. 发明申请

US20050116357A1 METHOD AND STRUCTURE TO ENHANCE TEMPERATURE/HUMIDITY/BIAS PERFORMANCE OF SEMICONDUCTOR DEVICES BY SURFACE MODIFICATION 失效
标题翻译：通过表面改性提高半导体器件的温度/湿度/偏差性能的方法和结构
公开(公告)号：US20050116357A1
公开(公告)日：2005-06-02
申请号：US10906189
申请日：2005-02-08
申请人： John Fitzsimmons , Stephen Gates , Michael Lane , Eric Liniger
发明人： John Fitzsimmons , Stephen Gates , Michael Lane , Eric Liniger
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/50 , H01L23/00 , H01L23/28
CPC分类号： H01L23/564 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.
摘要翻译：公开了一种修复半导体芯片（例如高速半导体微处理器，专用集成电路（ASIC））和其它高速集成电路器件（特别是使用低k电介质材料的器件）的引线键合损坏的方法。该方法涉及使用反应性液体的表面改性。在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。

7. 发明申请

US20080079176A1 METHOD AND STRUCTURE TO ENHANCE TEMPERATURE/HUMIDITY/BIAS PERFORMANCE OF SEMICONDUCTOR DEVICES BY SURFACE MODIFICATION 审中-公开
标题翻译：通过表面改性提高半导体器件的温度/湿度/偏差性能的方法和结构
公开(公告)号：US20080079176A1
公开(公告)日：2008-04-03
申请号：US11954966
申请日：2007-12-12
申请人： John Fitzsimmons , Stephen Gates , Michael Lane , Eric Liniger
发明人： John Fitzsimmons , Stephen Gates , Michael Lane , Eric Liniger
IPC分类号： H01L23/49
CPC分类号： H01L23/564 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.
摘要翻译：公开了一种修复半导体芯片（例如高速半导体微处理器，专用集成电路（ASIC））和其它高速集成电路器件（特别是使用低k电介质材料的器件）的引线键合损伤的方法。该方法涉及使用反应性液体的表面改性。在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。

8. 发明申请

US20060014376A1 Stacked via-stud with improved reliability in copper metallurgy 审中-公开
标题翻译：堆叠通孔，提高了铜冶金的可靠性
公开(公告)号：US20060014376A1
公开(公告)日：2006-01-19
申请号：US11230841
申请日：2005-09-20
申请人： Birendra Agarwala , Conrad Barile , Hormazdyar Dalal , Brett Engel , Michael Lane , Ernest Levine , Xiao Liu , Vincent McGahay , John McGrath , Conal Murray , Jawahar Nayak , Du Nguyen , Hazara Rathore , Thomas Shaw
发明人： Birendra Agarwala , Conrad Barile , Hormazdyar Dalal , Brett Engel , Michael Lane , Ernest Levine , Xiao Liu , Vincent McGahay , John McGrath , Conal Murray , Jawahar Nayak , Du Nguyen , Hazara Rathore , Thomas Shaw
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/31
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76829 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.
摘要翻译：一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织互连级别，从而增加互连级别之间堆叠通孔的灵活性。

9. 发明授权

US08101236B2 Method of fabricating a SiCOH dielectric material with improved toughness and improved Si-C bonding 有权
标题翻译：制造具有改进的韧性和改善的Si-C键合的SiCOH介电材料的方法
公开(公告)号：US08101236B2
公开(公告)日：2012-01-24
申请号：US12355316
申请日：2009-01-16
申请人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
发明人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
IPC分类号： C23C16/40
CPC分类号： H01L31/103 , Y10T428/31663
摘要： A method of fabricating a low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided. The method includes the deposition of the dielectric material from a first precursor which is an carbosilane or an alkoxycarbosilane molecule.
摘要翻译：提供了一种制造具有增强的内聚强度的低k电介质材料的方法，用于包括互连和感测结构在内的电子结构中。该方法包括从作为碳硅烷或烷氧基碳硅烷分子的第一前体沉积电介质材料。

10. 发明授权

US06764774B2 Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same 有权
标题翻译：具有对含Si和C的电介质的粘附性提高的结构及其制备方法
公开(公告)号：US06764774B2
公开(公告)日：2004-07-20
申请号：US10174748
申请日：2002-06-19
申请人： Alfred Grill , Michael Lane , Vishnubhai V. Patel
发明人： Alfred Grill , Michael Lane , Vishnubhai V. Patel
IPC分类号： H01L2912
CPC分类号： H01L23/53295 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10T428/12528 , Y10T428/12674 , Y10T428/24926 , H01L2924/00
摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer of dielectric material; a second layer of material selected from the group including: amorphous Silicon (a-Si), amorphous Ge (a-Ge) or alloys thereof, located on top of the first layer; and, a third layer located on top of the a-Si, a-Ge, or alloys thereof layer, wherein the second layer provides adhesion between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective a-Si, a-Ge, or alloys thereof bonding layers disposed to enhance adhesion between the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the adhesion between different dielectric is enhanced by an intermediate a-Si, a-Ge, or alloys thereof bonding layer. The thin a-Si, a-Ge, or alloys thereof layer may be hydrogenated or non-hydrogenated, or even partially oxidized.
摘要翻译：半导体器件结构和制造方法包括：具有顶部第一介电材料层的衬底; 选自包括位于第一层顶部的非晶硅（a-Si），无定形Ge（a-Ge）或其合金的第二层材料; 以及位于a-Si，a-Ge或其合金层的顶部上的第三层，其中第二层提供结构的第一和第三层之间的粘附。此外，半导体器件结构和制造方法包括绝缘结构，其包括多个电介质层和导电层，其各自的a-Si，a-Ge或其合金被设置以增强不同层之间的粘附。此外，电子器件结构在后端（“BEOL”）布线结构中包括绝缘和导电材料层作为嵌入式或层间电介质，其中不同电介质之间的粘附通过中间a- Si，a-Ge或其合金结合层。薄的a-Si，a-Ge或其合金层可以被氢化或非氢化，或甚至部分氧化。

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