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    • 10. 发明授权
    • Single stage dynamic receiver/decoder
    • 单级动态接收机/解码器
    • US5640108A
    • 1997-06-17
    • US486220
    • 1995-06-07
    • Christopher P. Miller
    • Christopher P. Miller
    • H03K19/173H03K19/0175
    • H03K19/1737
    • A high performance receiver/decoder circuit combines input signal detection and decoding to a one-of-n selection signal in a single stage. Particularly when implemented in dynamic logic, speed of decoding is substantially increased while reset and precharge circuits and procedures are greatly simplified which is accomplished by placing logic trees in series with a latch circuit and a common connection to a transistor or other circuit for enabling input evaluation. The decoder is preferably implemented with a plurality of identical circuits with true and complement inputs selectively distributed thereto, as may be convenient to the circuit design.
    • 高性能接收机/解码器电路将输入信号检测和解码结合到单级中的一个n选择信号。 特别是当在动态逻辑中实现时,解码速度显着增加,而复位和预充电电路和过程被大大简化,这是通过将逻辑树与锁存电路和与晶体管或其他电路的公共连接串联放置来实现的,以实现输入评估 。 解码器优选地用多个相同的电路实现,其中选择性地分配有真实和补码输入,这可能对于电路设计是方便的。