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1. 发明授权

US5566344A In-system programming architecture for a multiple chip processor 失效
标题翻译：用于多芯片处理器的系统内编程架构
公开(公告)号：US5566344A
公开(公告)日：1996-10-15
申请号：US445006
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Richard E. Crippen , Robert M. Salter, III
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Richard E. Crippen , Robert M. Salter, III
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。处理器可以在内部或外部进行编程。在系统内编程模式下，处理器程序计数器用于从处理器管芯上的板载ROM指令存储器中获取运行指令。处理器内核在其输出数据总线上输出要编程数据的地址。然后，处理器核心从外部设备接收要被编程到所选择的地址中的数据，并将其串行地输出到数据总线上并从其输出到存储器管芯。然后，地址和程序数据与存储器管芯上的单独寄存器一起并行输出，并且与编程脉冲一起编程存储器内核。

2. 发明授权

US5606710A Multiple chip package processor having feed through paths on one die 失效
标题翻译：多芯片封装处理器具有一个管芯上的馈通通路
公开(公告)号：US5606710A
公开(公告)日：1997-02-25
申请号：US359417
申请日：1994-12-20
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F13/00
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。在非易失性存储器管芯上提供多个馈通以提供从处理器管芯到非易失性存储器管芯相对于处理器管芯的阴影中的封装焊盘的通信路径，从而防止从处理器裸片到封装垫。在正常运行模式下，这些焊盘专门用作馈通，提供处理器管芯上的特定焊盘与封装上的特定焊盘之间的直接连接。然而，在其他操作模式中，从（或输出到）馈通封装焊盘输入的信号通过传输门被重新路由到非易失性存储器管芯。

3. 发明授权

US5598573A Multiple chip processor architecture with reset intercept circuit 失效
标题翻译：具有复位截止电路的多芯片处理器架构
公开(公告)号：US5598573A
公开(公告)日：1997-01-28
申请号：US446018
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , David W. Weinrich , Robert M. Salter, III
发明人： Christopher M. Hall , Gary D. Phillips , David W. Weinrich , Robert M. Salter, III
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。复位截止电路设置在非易失性存储器管芯上，用于截取从多芯片封装的外部提供给非易失性存储器管芯的复位输入的信号。复位截取电路将其修改版本提供给处理器管芯。特别地，复位截取电路响应于接收到复位信号时的多芯片封装的当前工作模式，执行将复位信号的修改版本发送到处理器管芯的功能。

4. 发明授权

US5623686A Non-volatile memory control and data loading architecture for multiple chip processor 失效
标题翻译：用于多芯片处理器的非易失性存储器控制和数据加载架构
公开(公告)号：US5623686A
公开(公告)日：1997-04-22
申请号：US446079
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。非易失性存储器管芯上的输入数据寄存器和相关的多路复用器允许根据操作模式将来自不同源的数据加载到输入数据寄存器中。此外，输入数据寄存器的输出耦合到多个位置，使得数据的目的地也可以响应于操作模式而被切换。特别地，输入数据寄存器的输出耦合到输出端口，程序数据寄存器（程序数据可以通过其加载到程序存储器中）和控制寄存器，用于设置用于执行特定完整性测试的各种控制位，在制造之后执行。因此，输入数据寄存器用于从外部源编程存储器，从外部设备设置控制位，并将数据从处理器发送到R端口并传输到外部设备。

5. 发明授权

US5581779A Multiple chip processor architecture with memory interface control register for in-system programming 失效
标题翻译：具有存储器接口控制寄存器的多芯片处理器架构，用于在系统编程
公开(公告)号：US5581779A
公开(公告)日：1996-12-03
申请号：US445007
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。处理器包括分别包括处理器管芯和存储管芯上的第一和第二存储器接口控制寄存器的系统内编程模式，用于从处理器核心接收控制位以控制管芯上的多路复用器。第一存储器接口控制寄存器的各个位输出线耦合到多路复用器的控制输入端。

6. 发明授权

US5613144A Serial register multi-input multiplexing architecture for multiple chip processor 失效
标题翻译：串行寄存器多输入复用架构，适用于多芯片处理器
公开(公告)号：US5613144A
公开(公告)日：1997-03-18
申请号：US444532
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , David W. Weinrich
发明人： Christopher M. Hall , Gary D. Phillips , David W. Weinrich
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。

7. 发明授权

US5218564A Layout efficient 32-bit shifter/register with 16-bit interface 失效
标题翻译：布局高效的32位移位器/ 16位接口寄存器
公开(公告)号：US5218564A
公开(公告)日：1993-06-08
申请号：US712208
申请日：1991-06-07
申请人： Ralph W. Haines , Gary D. Phillips , D. Kevin Covey , Thomas W. S. Thomson
发明人： Ralph W. Haines , Gary D. Phillips , D. Kevin Covey , Thomas W. S. Thomson
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53 , G06F7/544 , G06F9/38 , G06F12/08
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.

8. 发明授权

US5311458A CPU with integrated multiply/accumulate unit 失效
标题翻译：具有集成乘法/累加单元的CPU
公开(公告)号：US5311458A
公开(公告)日：1994-05-10
申请号：US975399
申请日：1992-11-10
申请人： Ralph W. Haines , Gary D. Phillips , D. Kevin Covey , Thomas W. S. Thomson
发明人： Ralph W. Haines , Gary D. Phillips , D. Kevin Covey , Thomas W. S. Thomson
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53 , G06F7/544 , G06F9/38 , G06F12/08 , G06F7/38
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.
摘要翻译：公开了一种集成电路（IC）处理器架构，其实现具有较少的数字改进速度和更有效的布局的硬件，信号处理（DSP）功能。中央处理单元（CPU）的资源与集成乘法/累加单元结合使用以执行DSP操作。 CPU的内部寄存器用于存储引用循环采样缓冲区的指针。 CPU因此管理从采样缓冲器到乘法/累加单元的系数的选择和传送，从而允许将最低数量的较低速度的硬件用于乘法/累加单元，并允许与CPU并行执行DSP操作操作。

9. 发明授权

US5319588A Signed overflow sticky bits 失效
标题翻译：签名溢出粘性位
公开(公告)号：US5319588A
公开(公告)日：1994-06-07
申请号：US987617
申请日：1992-12-09
申请人： Ralph W. Haines , Gary D. Phillips , D. Kevin Covey , Thomas W. S. Thomson
发明人： Ralph W. Haines , Gary D. Phillips , D. Kevin Covey , Thomas W. S. Thomson
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53 , G06F7/544 , G06F9/38 , G06F12/08 , G06F7/38
CPC分类号： G06F7/5338 , G06F7/5443 , G06F9/3877 , G06F2207/3876 , G06F7/4991 , G06F7/49921
摘要： An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow. The sticky flag bits have mutually exclusive true states in that once a flag bit has been set true, the other flag bit cannot be set true until both flag bits have been specifically reset.
摘要翻译：用于乘法和累加有符号二进制数据并指示有符号算术溢出发生的算术单元包括乘法器累加器和溢出标志寄存器。乘法器 - 累加器接收和选择性地倍数并累加有符号的二进制数据，并且提供表示乘法和累积数据的输出数据和表示其极性的符号位，即正或负。标志寄存器提供两个“粘性”标志位，用于指示已经发生乘法和累加数据的带符号算术溢出（正或负）。标志位是“粘性”，因为一旦设置了一个标志，它就不能被另一个算术溢出条件复位。相反，它必须特别重置。符号位用于选择性地将两个粘性标志位中的一个设置为真实状态，以指示第一个算术溢出的方向（正或负）。粘标志位具有相互排除的真实状态，因为一旦标志位被设置为真，则在两个标志位被特别复位之前，另一个标志位不能被设置为真。

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