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1. 发明授权

US5566344A In-system programming architecture for a multiple chip processor 失效
标题翻译：用于多芯片处理器的系统内编程架构
公开(公告)号：US5566344A
公开(公告)日：1996-10-15
申请号：US445006
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Richard E. Crippen , Robert M. Salter, III
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Richard E. Crippen , Robert M. Salter, III
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。处理器可以在内部或外部进行编程。在系统内编程模式下，处理器程序计数器用于从处理器管芯上的板载ROM指令存储器中获取运行指令。处理器内核在其输出数据总线上输出要编程数据的地址。然后，处理器核心从外部设备接收要被编程到所选择的地址中的数据，并将其串行地输出到数据总线上并从其输出到存储器管芯。然后，地址和程序数据与存储器管芯上的单独寄存器一起并行输出，并且与编程脉冲一起编程存储器内核。

2. 发明授权

US5606710A Multiple chip package processor having feed through paths on one die 失效
标题翻译：多芯片封装处理器具有一个管芯上的馈通通路
公开(公告)号：US5606710A
公开(公告)日：1997-02-25
申请号：US359417
申请日：1994-12-20
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F13/00
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。在非易失性存储器管芯上提供多个馈通以提供从处理器管芯到非易失性存储器管芯相对于处理器管芯的阴影中的封装焊盘的通信路径，从而防止从处理器裸片到封装垫。在正常运行模式下，这些焊盘专门用作馈通，提供处理器管芯上的特定焊盘与封装上的特定焊盘之间的直接连接。然而，在其他操作模式中，从（或输出到）馈通封装焊盘输入的信号通过传输门被重新路由到非易失性存储器管芯。

3. 发明授权

US5623686A Non-volatile memory control and data loading architecture for multiple chip processor 失效
标题翻译：用于多芯片处理器的非易失性存储器控制和数据加载架构
公开(公告)号：US5623686A
公开(公告)日：1997-04-22
申请号：US446079
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。非易失性存储器管芯上的输入数据寄存器和相关的多路复用器允许根据操作模式将来自不同源的数据加载到输入数据寄存器中。此外，输入数据寄存器的输出耦合到多个位置，使得数据的目的地也可以响应于操作模式而被切换。特别地，输入数据寄存器的输出耦合到输出端口，程序数据寄存器（程序数据可以通过其加载到程序存储器中）和控制寄存器，用于设置用于执行特定完整性测试的各种控制位，在制造之后执行。因此，输入数据寄存器用于从外部源编程存储器，从外部设备设置控制位，并将数据从处理器发送到R端口并传输到外部设备。

4. 发明授权

US5581779A Multiple chip processor architecture with memory interface control register for in-system programming 失效
标题翻译：具有存储器接口控制寄存器的多芯片处理器架构，用于在系统编程
公开(公告)号：US5581779A
公开(公告)日：1996-12-03
申请号：US445007
申请日：1995-05-19
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
IPC分类号： G06F15/78 , G11C16/10 , G06F15/76
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.
摘要翻译：一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能的操作和其他控制信号。处理器包括分别包括处理器管芯和存储管芯上的第一和第二存储器接口控制寄存器的系统内编程模式，用于从处理器核心接收控制位以控制管芯上的多路复用器。第一存储器接口控制寄存器的各个位输出线耦合到多路复用器的控制输入端。

5. 发明授权

US06118439A Low current voltage supply circuit for an LCD driver 失效
标题翻译：用于LCD驱动器的低电流电压电路
公开(公告)号：US06118439A
公开(公告)日：2000-09-12
申请号：US21674
申请日：1998-02-10
申请人： Franklin S. Ho , William E. Miller , Ying Quan Zhong , Richard E. Crippen
发明人： Franklin S. Ho , William E. Miller , Ying Quan Zhong , Richard E. Crippen
IPC分类号： G09G3/18 , G09G3/36 , G09G5/00
CPC分类号： G09G3/18 , G09G3/3696 , G09G2320/0252 , G09G2330/022
摘要： A voltage supply circuit for an LCD driver employs two voltage dividers. A low current voltage divider includes resistive elements having a high resistance, thus providing a bias voltage with a low current. A high current voltage divider includes resistive elements having low resistances, thus providing a bias voltage with a high current. The high current voltage divider provides bias voltage levels with high current at the beginning of each time phase change. Thus, the liquid crystal display receives a high current when updating the bias voltage levels on the LCD, thereby producing a fast settling time. When the bias voltage levels are held constant, however, only the low current voltage divider provides the bias voltage levels to reduce power consumption. A halt mode prevents the liquid crystal display and driver from consuming any power by disconnecting both voltage dividers from the voltage source when in sleep mode. A voltage drop mode produces a reduction in the bias voltage levels by placing another voltage drop in series with the voltage dividers.
摘要翻译：用于LCD驱动器的电压供应电路采用两个分压器。低电流分压器包括具有高电阻的电阻元件，从而提供具有低电流的偏置电压。高电流分压器包括具有低电阻的电阻元件，从而提供具有高电流的偏置电压。高电流分压器在每次相变开始时提供高电流的偏置电压电平。因此，当更新LCD上的偏置电压电平时，液晶显示器接收高电流，从而产生快速建立时间。然而，当偏置电压电平保持不变时，只有低电流分压器才提供偏置电压电平以降低功耗。停止模式通过在睡眠模式下从电压源断开两个分压器来防止液晶显示器和驱动器消耗任何电力。通过与分压器串联放置另一个电压降，电压降模式产生偏置电压电平的降低。

6. 发明授权

US5657444A Microprocessor with secure programmable read only memory circuit 失效
标题翻译：具有安全可编程只读存储器电路的微处理器
公开(公告)号：US5657444A
公开(公告)日：1997-08-12
申请号：US510831
申请日：1995-08-03
申请人： Christopher M. Hall , William E. Miller
发明人： Christopher M. Hall , William E. Miller
IPC分类号： G06F21/00 , G11C8/20 , G11C16/22 , H04L12/22
CPC分类号： G06F21/79 , G11C16/22 , G11C8/20
摘要： A microprocessor which has a secure read only memory is disclosed. The secure read only memory provides for storage of a program and security to protect that program.
摘要翻译：公开了一种具有安全的只读存储器的微处理器。安全的只读存储器用于存储程序和安全性以保护该程序。

7. 发明授权

US07668445B2 Apparatus and method for detecting condition of a heating element 有权
标题翻译：用于检测加热元件状态的装置和方法
公开(公告)号：US07668445B2
公开(公告)日：2010-02-23
申请号：US11495067
申请日：2006-07-28
申请人： William E. Miller , Lawrence J. Brazis
发明人： William E. Miller , Lawrence J. Brazis
IPC分类号： H05B3/80
CPC分类号： F24H9/2021 , H05B1/0283
摘要： A control for an electric water heater detects a condition of a heating element when the heating element is not being energized. A switching module is operable to interrupt power to the heating element, which de-energizes the heating element. A detector module detects the condition of the heating element when the heating element is de-energized. The detector module senses current flowing through the heating element and generates a detection signal that is indicative of the current.
摘要翻译：当加热元件未通电时，电热水器的控制器检测加热元件的状态。开关模块可操作以中断加热元件的电力，这使加热元件断电。当加热元件断电时，检测器模块检测加热元件的状态。检测器模块感测流过加热元件的电流并产生指示电流的检测信号。

8. 发明授权

US07049523B2 Separable multi-member composite cable 有权
标题翻译：可分离多组合复合电缆
公开(公告)号：US07049523B2
公开(公告)日：2006-05-23
申请号：US10233287
申请日：2002-08-30
申请人： Brian R. Shuman , Thomas L. Rodeghero , Galen M. Gareis , William E. Miller , Charles R. Barnett
发明人： Brian R. Shuman , Thomas L. Rodeghero , Galen M. Gareis , William E. Miller , Charles R. Barnett
IPC分类号： H01B11/00
CPC分类号： H01B11/1891 , G02B6/441 , G02B6/4417 , H01B7/0045 , H01B11/20 , H01B11/22 , H01B13/14 , H01B13/24 , H02G3/0487 , Y10T29/49194 , Y10T29/49201
摘要： Multi-member cables which are comprised of two or more components (including component cables and non-cable components) held together by at least one adhesive element placed between the components, and methods for manufacturing such cables. Multi-member cables which are comprised of jacketed cables whose jackets are adhered together without the use of an adhesive element, such as by co-forming the jackets, and methods for manufacturing such cables are also discussed. Generally, the components will be separated from the multi-member cable by an installer, although other methods may also be used.
摘要翻译：由两个或更多个组件（包括部件电缆和非电缆部件）组成的多构件电缆，其由放置在部件之间的至少一个粘合剂元件保持在一起，以及用于制造这种电缆的方法。还讨论了由夹套电缆组成的多构件电缆，其夹套粘合在一起而不使用粘合元件，例如通过共同成形夹套，以及用于制造这种电缆的方法。通常，组件将通过安装者与多构件电缆分离，尽管也可以使用其他方法。

9. 发明授权

US07011736B1 U+4 generation in HTER 失效
标题翻译： U + 4代
公开(公告)号：US07011736B1
公开(公告)日：2006-03-14
申请号：US10637089
申请日：2003-08-05
申请人： William E. Miller , Eddie C. Gay , Zygmunt Tomczuk
发明人： William E. Miller , Eddie C. Gay , Zygmunt Tomczuk
IPC分类号： C25C3/34
CPC分类号： C25C3/34 , C25C7/005
摘要： A improved device and process for recycling spent nuclear fuels, in particular uranium metal, that facilitates the refinement and recovery of uranium metal from spent metallic nuclear fuels. The electrorefiner device comprises two anodes in predetermined spatial relation to a cathode. The anodese have separate current and voltage controls. A much higher voltage than normal for the electrorefining process is applied to the second anode, thereby facilitating oxidization of uranium (III), U+, to uranium (IV), U+4. The current path from the second anode to the cathode is physically shorter than the similar current path from the second anode to the spent nuclear fuel contained in a first anode shaped as a basket. The resulting U+4 oxidizes and solubilizes rough uranium deposited on the surface of the cathode. A softer uranium metal surface is left on the cathode and is more readily removed by a scraper.
摘要翻译：用于回收废核燃料，特别是铀金属的改进装置和方法，其有助于从废金属核燃料中精炼和回收铀金属。电学纯化装置包括与阴极预定的空间关系的两个阳极。阳极电池具有单独的电流和电压控制。对于第二阳极施加比正常电压高的电解精炼工艺，因此铀（III），铀（Ⅳ），铀（Ⅳ），U + 4， SUP>。从第二阳极到阴极的电流路径物理上短于从第二阳极到包含在形成为篮状物的第一阳极中的废核燃料的类似电流路径。所产生的U + 4氧化并溶解沉积在阴极表面上的粗铀。较软的铀金属表面留在阴极上，更容易被刮刀去除。

10. 发明授权

US5711019A Method for treating electrolyte to remove Li.sub.2 O 失效
标题翻译：处理电解液以除去Li2O的方法
公开(公告)号：US5711019A
公开(公告)日：1998-01-20
申请号：US594974
申请日：1996-01-31
申请人： Zygmunt Tomczuk , William E. Miller , Gerald K. Johnson , James L. Willit
发明人： Zygmunt Tomczuk , William E. Miller , Gerald K. Johnson , James L. Willit
IPC分类号： A62D3/00 , A62D3/37 , A62D101/43 , C01D3/14 , C01D15/00
CPC分类号： A62D3/37 , C01D15/00 , C01D3/14 , A62D2101/43
摘要： A method of removing Li.sub.2 O present in an electrolyte predominantly of LiCl and KCl. The electrolyte is heated to a temperature not less than about 500.degree. C. and then Al is introduced into the electrolyte in an amount in excess of the stoichiometric amount needed to convert the Li.sub.2 O to a Li-Al alloy and lithium aluminate salt. The salt and aluminum are maintained in contact with agitation for a time sufficient to convert the Li.sub.2 O.
摘要翻译：一种除去Li2O和KCl主要存在于电解质中的Li2O的方法。将电解质加热至不低于约500℃的温度，然后将Al以超过将Li 2 O转化为Li-Al合金和铝酸锂盐所需的化学计量的量引入电解质中。盐和铝保持与搅拌接触足够的时间以转化Li 2 O。

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