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1. 发明授权

US07007036B2 Method and apparatus for embedding configuration data 失效
公开(公告)号：US07007036B2
公开(公告)日：2006-02-28
申请号：US10109285
申请日：2002-03-28
申请人： Christopher J. McCarty , Stephen B. Johnson , Brad D. Besmer
发明人： Christopher J. McCarty , Stephen B. Johnson , Brad D. Besmer
IPC分类号： G06F7/00
CPC分类号： G06F9/44505 , Y10S707/99931 , Y10S707/99943
摘要： The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

2. 发明授权

US06842792B2 Method and/or apparatus to sort request commands for SCSI multi-command packets 有权
标题翻译：用于对SCSI多命令分组的请求命令进行排序的方法和/或装置
公开(公告)号：US06842792B2
公开(公告)日：2005-01-11
申请号：US10183670
申请日：2002-06-27
申请人： Stephen B. Johnson , Bradley D. Besmer , Guy W. Kendall , Christopher J. McCarty , Andrew C. Brown
发明人： Stephen B. Johnson , Bradley D. Besmer , Guy W. Kendall , Christopher J. McCarty , Andrew C. Brown
IPC分类号： G06F3/00 , G06F13/12 , G06F13/14
CPC分类号： G06F13/126
摘要： An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.
摘要翻译：一种包括多个IO队列和逻辑电路的装置。多个IO队列可以被配置为接收相应的IO请求并响应于触发信号呈现IO请求。逻辑电路可以被配置为：（i）（i）响应于IO请求的相应设备标识（ID），接收IO请求中的一个或多个并且（ii）串行地合并IO请求，以及（iii）呈现一个或多个合并的IO请求作为响应于触发信号的一个或多个相应的上下文队列请求，以及（b）当当前队列计数等于最大队列深度时产生触发信号。

3. 发明授权

US06629229B1 Message index descriptor 失效
标题翻译：消息索引描述符
公开(公告)号：US06629229B1
公开(公告)日：2003-09-30
申请号：US09864760
申请日：2001-05-24
申请人： Christopher J. McCarty , Stephen B. Johnson
发明人： Christopher J. McCarty , Stephen B. Johnson
IPC分类号： G06F1202
CPC分类号： G06F13/387
摘要： A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.
摘要翻译：包括存储器，队列和转换器的电路。存储器可以被配置为在至少与基地址一样大的地址处存储消息。队列可以被配置为存储描述符，其中描述符被配置为具有（i）索引，（ii）路由字段，和（iii）比地址少的比特。翻译器可以被配置为在地址和索引之间进行转换。

4. 发明授权

US07111301B1 Request and completion queue load balancing 有权
标题翻译：请求和完成队列负载均衡
公开(公告)号：US07111301B1
公开(公告)日：2006-09-19
申请号：US09972330
申请日：2001-10-05
申请人： Stephen B. Johnson , Christopher J. McCarty
发明人： Stephen B. Johnson , Christopher J. McCarty
IPC分类号： G06F9/46 , G06F3/06
CPC分类号： H04L49/901 , H04L47/125 , H04L49/90
摘要： An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.
摘要翻译：一种包括第一电路，第二电路和第三电路的装置。第一电路可以被配置为响应于请求头指针和请求尾指针来生成请求计数。第二电路可以被配置为响应于完成头指针和完成尾指针来产生完成计数。第三电路可以被配置为响应于请求和完成计数来对中断进行优先级排序。

5. 发明授权

US06868492B1 Methods and apparatus for booting a host adapter device devoid of nonvolatile program memory 失效
标题翻译：用于引导没有非易失性程序存储器的主机适配器设备的方法和装置
公开(公告)号：US06868492B1
公开(公告)日：2005-03-15
申请号：US09910088
申请日：2001-07-20
申请人： Christopher J. McCarty , Stephen B. Johnson
发明人： Christopher J. McCarty , Stephen B. Johnson
IPC分类号： G06F9/445
CPC分类号： G06F9/4411
摘要： Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.
摘要翻译：用于在主机适配器设备没有用于存储可在智能主机适配器设备中操作的编程指令的独立的非易失性存储器设备的系统中引导主机适配器设备的方法和相关联的结构。智能主机适配器设备的操作编程指令与系统的标准BIOS代码一起存储在系统主板的非易失性存储器中。然后，智能主机适配器设备的操作编程指令通过BIOS代码下载到主机适配器的易失性本地程序存储器中，以初始化智能主机适配器设备的操作。此外，可在主板上的操作系统中操作的设备驱动程序代码将从智能主机适配器上载先前下载的编程指令，使得编程指令可以响应于复位条件，电源管理事件和其他条件被重新加载到主机适配器。

6. 发明授权

US06173341B2 System and method for configuring adapters in a computer system 有权
标题翻译：用于在计算机系统中配置适配器的系统和方法
公开(公告)号：US06173341B2
公开(公告)日：2001-01-09
申请号：US09140040
申请日：1998-08-26
申请人： Theodore F. Emerson , Christopher J. McCarty
发明人： Theodore F. Emerson , Christopher J. McCarty
IPC分类号： G06F1300
CPC分类号： G06F9/4411
摘要： A computer system with an Intelligent Input/Output architecture having a plug-and-play control mechanism for assigning and controlling one or more adapters. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices or adapters operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. Initially, a selected adapter is defaulted to an “assigned” state without changing the interrupt routing associated with the adapter. Upon detecting the presence of a driver module that is executable on the IOP, the assigned adapter is marked as “controlled” and the interrupt routing is configured to deliver interrupts to the IOP. Subsequently, the controlled adapter is rendered “hidden” from the host operating system.
摘要翻译：具有智能输入/输出架构的计算机系统具有用于分配和控制一个或多个适配器的即插即用控制机构。计算机系统包括用于执行主机操作系统的主机处理器，设置在主机总线上的主机处理器，经由主机到总线桥接器可操作地耦合到主机总线的输入/输出（I / O）总线，以及可操作地连接到I / O总线的用于在由IOP资源控制的I / O事务中传送数据的多个外围设备或适配器。最初，所选择的适配器默认为“分配”状态，而不改变与适配器相关联的中断路由。在检测到可在IOP上执行的驱动器模块的存在时，所分配的适配器被标记为“受控”，并且中断路由被配置为将中断传送到IOP。随后，受控适配器从主机操作系统“隐藏”。

7. 发明授权

US06212587B1 Device proxy agent for hiding computing devices on a computer bus 失效
标题翻译：用于在计算机总线上隐藏计算设备的设备代理
公开(公告)号：US06212587B1
公开(公告)日：2001-04-03
申请号：US08988345
申请日：1997-12-10
申请人： Theodore F. Emerson , Christopher J. McCarty
发明人： Theodore F. Emerson , Christopher J. McCarty
IPC分类号： G06F1338
CPC分类号： G06F12/06
摘要： A system for hiding computing devices on a computer bus comprising a computer memory for storing information pertaining to computing devices, a device proxy agent for reserving memory for storing information pertaining to hidden devices and an IOP, which in conjunction with the device proxy agent, assigns the memory space assigned to the device proxy agent to hidden devices. A section of memory is allocated as memory address space for the computer bus. A first portion of the allocated memory address space is assigned to non-hidden computing devices and a second portion of the allocated memory address space is assigned to the device proxy agent. The IOP in conjunction with the device proxy agent assigns the memory address space assigned to the device proxy agent to the hidden devices.
摘要翻译：一种用于在计算机总线上隐藏计算设备的系统，包括用于存储与计算设备相关的信息的计算机存储器，用于存储与隐藏设备有关的信息的存储器的设备代理代理和与设备代理代理相结合的IOP 分配给设备代理的内存空间到隐藏设备。一段内存被分配为计算机总线的存储器地址空间。分配的存储器地址空间的第一部分被分配给非隐藏的计算设备，并且分配的存储器地址空间的第二部分被分配给设备代理。 IOP与设备代理代理一起将分配给设备代理的内存地址空间分配给隐藏的设备。

8. 发明授权

US07689744B1 Methods and structure for a SAS/SATA converter 有权
标题翻译： SAS / SATA转换器的方法和结构
公开(公告)号：US07689744B1
公开(公告)日：2010-03-30
申请号：US11082673
申请日：2005-03-17
申请人： Christopher J. McCarty , Margit C. Evensta , Timothy E. Hoglund
发明人： Christopher J. McCarty , Margit C. Evensta , Timothy E. Hoglund
IPC分类号： G06F13/38
CPC分类号： G06F13/4045
摘要： Methods and structure for enabling transparent coordination between multiple host systems sharing access to a common SATA storage device to improve bandwidth utilization therebetween in a manner transparent to each of the multiple host systems. The SAS protocol may be utilized by each of the host systems coupled to an SAS/SATA Converter. The storage device coupled to an output path of the SAS/SATA Converter is selectively coupled to one of the multiple host systems each coupled to an input signal path of the SAS/SATA Converter to the shared SATA storage device. Protocol conversion within the SAS/SATA Converter may convert between host SAS protocol exchanges and SATA protocol exchanges of the storage device. Other features within the SAS/SATA Converter may provide queuing or buffering of SAS protocol exchanges from a host system presently non-selected for coupling to the shared SATA storage device.
摘要翻译：共享对公共SATA存储设备的访问的多个主机系统之间的透明协调的方法和结构，以便以对多个主机系统中的每一个透明的方式提高它们之间的带宽利用率。 SAS协议可以被耦合到SAS / SATA转换器的每个主机系统使用。耦合到SAS / SATA转换器的输出路径的存储设备选择性地耦合到多个主机系统之一，每个主机系统耦合到SAS / SATA转换器的输入信号路径到共享的SATA存储设备。 SAS / SATA转换器内的协议转换可以在主机SAS协议交换和存储设备的SATA协议交换之间进行转换。 SAS / SATA转换器中的其他功能可以提供来自当前未选择用于耦合到共享SATA存储设备的主机系统的SAS协议交换的排队或缓冲。

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