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1. 发明授权

US06842792B2 Method and/or apparatus to sort request commands for SCSI multi-command packets 有权
标题翻译：用于对SCSI多命令分组的请求命令进行排序的方法和/或装置
公开(公告)号：US06842792B2
公开(公告)日：2005-01-11
申请号：US10183670
申请日：2002-06-27
申请人： Stephen B. Johnson , Bradley D. Besmer , Guy W. Kendall , Christopher J. McCarty , Andrew C. Brown
发明人： Stephen B. Johnson , Bradley D. Besmer , Guy W. Kendall , Christopher J. McCarty , Andrew C. Brown
IPC分类号： G06F3/00 , G06F13/12 , G06F13/14
CPC分类号： G06F13/126
摘要： An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.
摘要翻译：一种包括多个IO队列和逻辑电路的装置。多个IO队列可以被配置为接收相应的IO请求并响应于触发信号呈现IO请求。逻辑电路可以被配置为：（i）（i）响应于IO请求的相应设备标识（ID），接收IO请求中的一个或多个并且（ii）串行地合并IO请求，以及（iii）呈现一个或多个合并的IO请求作为响应于触发信号的一个或多个相应的上下文队列请求，以及（b）当当前队列计数等于最大队列深度时产生触发信号。

2. 发明授权

US06810448B1 Method and apparatus for processing chain messages (SGL chaining) 失效
标题翻译：处理链接消息的方法和装置（SGL链接）
公开(公告)号：US06810448B1
公开(公告)日：2004-10-26
申请号：US09848569
申请日：2001-05-02
申请人： Stephen B. Johnson , Timothy E. Hoglund , Guy W. Kendall
发明人： Stephen B. Johnson , Timothy E. Hoglund , Guy W. Kendall
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： A message-based I/O architecture comprising a list describing one or more source buffers and a message header. The list may be segmented in multiple memory locations. The message header may be configured to (i) indicate whether the list is segmented and (ii) provide information for linking the list when the list is segmented.
摘要翻译：基于消息的I / O架构，其包括描述一个或多个源缓冲器和消息头的列表。列表可以在多个存储器位置中分段。消息报头可以被配置为（i）指示列表是否被分段，并且（ii）在列表被分段时提供用于链接列表的信息。

3. 发明申请

US20080052574A1 Circuits and associated methods for improved debug and test of an application integrated circuit 失效
标题翻译：用于改进应用集成电路调试和测试的电路和相关方法
公开(公告)号：US20080052574A1
公开(公告)日：2008-02-28
申请号：US11508585
申请日：2006-08-23
申请人： Paul J. Smith , Brad D. Besmer , Guy W. Kendall
发明人： Paul J. Smith , Brad D. Besmer , Guy W. Kendall
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/31724
摘要： Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.
摘要翻译：用于测试应用集成电路内部操作的电路和相关方法。此处的特征和方面将可配置的测试中断电路添加到应用电路设计，以允许基于从监视应用电路的内部信号确定的条件从集成电路产生动态的可配置中断。可以测试和用于产生测试中断的内部信号是不暴露于集成电路的外部处理器接口的内部信号，因此可以被配置为基于集成电路的专用功能电路的任何内部状态进行中断。

4. 发明授权

US07617428B2 Circuits and associated methods for improved debug and test of an application integrated circuit 失效
标题翻译：用于改进应用集成电路调试和测试的电路和相关方法
公开(公告)号：US07617428B2
公开(公告)日：2009-11-10
申请号：US11508585
申请日：2006-08-23
申请人： Paul J. Smith , Brad D. Besmer , Guy W. Kendall
发明人： Paul J. Smith , Brad D. Besmer , Guy W. Kendall
IPC分类号： G01R31/28 , G06F7/02 , G06F13/24
CPC分类号： G01R31/31703 , G01R31/31724
摘要： Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.
摘要翻译：用于测试应用集成电路内部操作的电路和相关方法。此处的特征和方面将可配置的测试中断电路添加到应用电路设计，以允许基于从监视应用电路的内部信号确定的条件从集成电路产生动态的可配置中断。可以测试和用于产生测试中断的内部信号是不暴露于集成电路的外部处理器接口的内部信号，因此可以被配置为基于集成电路的专用功能电路的任何内部状态进行中断。

5. 发明授权

US06904481B1 Bus sequence operation with automatic linking from current I/O information to subsequent I/O information 失效
标题翻译：总线顺序操作，从当前I / O信息自动链接到后续I / O信息
公开(公告)号：US06904481B1
公开(公告)日：2005-06-07
申请号：US09834013
申请日：2001-04-12
申请人： Brad D. Besmer , Guy W. Kendall , Brian A. Day
发明人： Brad D. Besmer , Guy W. Kendall , Brian A. Day
IPC分类号： G06F13/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/385
摘要： In a computer system, a bus adapter processes bus operation information structures for performing bus operations by automatically starting processing each bus operation information structure after completing processing the previous bus operation information structure. A processor forms the bus operation information structures and sets control over each bus operation information structure to a sequencer for processing. When a next bus operation information structure is ready for processing after completing processing the previous bus operation information structure, the sequencer checks whether it has control over the next bus operation information structure, and if so, begins processing the next bus operation information structure without being instructed to do so by the processor.
摘要翻译：在计算机系统中，总线适配器处理总线操作信息结构以执行总线操作，通过在完成处理先前的总线操作信息结构之后自动开始处理每个总线操作信息结构。处理器形成总线操作信息结构，并且将对每个总线操作信息结构的控制设置到定序器以进行处理。当完成处理前一个总线操作信息结构的下一个总线操作信息结构准备好进行处理时，定序器检查它是否控制下一个总线操作信息结构，如果是，则开始处理下一个总线操作信息结构，而不会由处理器指示这样做。

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