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1. 发明授权

US08854121B2 Self-calibrating differential current circuit 有权
标题翻译：自校准差动电流电路
公开(公告)号：US08854121B2
公开(公告)日：2014-10-07
申请号：US13472537
申请日：2012-05-16
申请人： Abhishek Duggal
发明人： Abhishek Duggal
IPC分类号： H05K5/00
CPC分类号： G05F3/262
摘要： In one embodiment, a constant-current generator is connected in series with a dependent (e.g., tail) device. A switched capacitor circuit connected to the gate of the dependent device is operated to (i) charge at least one capacitor of the switched capacitor circuit, (ii) use the at least one charged capacitor to adjust the gate voltage of the dependent device to drive the dependent current through the dependent device to be equal to the constant current through the constant-current generator, and (iii) direct the dependent and constant currents through source and sink current nodes.
摘要翻译：在一个实施例中，恒定电流发生器与依赖（例如，尾部）装置串联连接。连接到从属装置的栅极的开关电容器电路被操作为（i）对开关电容器电路的至少一个电容器充电，（ii）使用至少一个充电电容器来调节从属装置的栅极电压以驱动通过相关器件的依赖电流等于通过恒流发生器的恒定电流，以及（iii）通过源极和吸收电流节点引导依赖和恒定的电流。

2. 发明申请

US20130234874A1 Digital-to-Analog Converter 有权
标题翻译：数模转换器
公开(公告)号：US20130234874A1
公开(公告)日：2013-09-12
申请号：US13415898
申请日：2012-03-09
申请人： James A. Bailey , Abhishek Duggal
发明人： James A. Bailey , Abhishek Duggal
IPC分类号： H03M1/66
CPC分类号： H03M1/822 , H03F3/2175 , H03F3/45475 , H03F3/45928 , H03M1/0682
摘要： A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.
摘要翻译：数模转换器（DAC）具有脉冲宽度编码器，其产生具有与DAC数字输入值成比例的脉冲宽度的充电脉冲。充电脉冲控制在充电脉冲期间选择性地将电流源连接到电容器的充电开关。在充电脉冲结束时，对应于存储在电容器中的电荷的电压形成DAC的模拟输出信号。这样的DAC可以在电容器上配置（1）负增益放大器，以形成负反馈回路，（2）具有多个并联电流源和/或（3）在差分架构中。

3. 发明授权

US08525574B1 Bootstrap switch circuit with over-voltage prevention 失效
标题翻译：自举开关电路具有过压保护功能
公开(公告)号：US08525574B1
公开(公告)日：2013-09-03
申请号：US13471659
申请日：2012-05-15
申请人： Abhishek Duggal
发明人： Abhishek Duggal
IPC分类号： H03K17/16
CPC分类号： H03K17/063 , G11C27/02 , H03K17/102 , H03K2217/0054
摘要： In one embodiment, a bootstrap switch circuit has (i) a switch device that selectively provides a input signal as an output signal and bootstrap circuitry that provides a relatively high-voltage control signal to the gate of the switch device to turn on the switch device while preventing any over-voltage conditions from being applied to the switch device. The bootstrap circuitry includes a capacitor and a number of transistors configured as either switches or inverters. The circuit has two operating phases: one in which the capacitor gets charged while the switch device is turned off and the other in which the charged capacitor is isolated and used to generate the high-voltage control signal to be a fixed voltage difference above the current voltage level of the input signal applied to the switch device, thereby preventing an over-voltage condition.
摘要翻译：在一个实施例中，自举开关电路具有（i）开关装置，其选择性地将输入信号提供为输出信号，以及自举电路，其向开关装置的栅极提供相对高压的控制信号以使开关装置同时防止任何过电压条件被施加到开关装置。引导电路包括电容器和配置为开关或逆变器的多个晶体管。该电路具有两个工作阶段：其中电容器在开关器件关断时被充电，另一个在充电电容器被隔离并且用于产生高电压控制信号的固定电压差施加到开关装置的输入信号的电压电平，从而防止过电压状态。

4. 发明授权

US07496780B2 Reduction of data skew in parallel processing circuits 有权
标题翻译：减少并行处理电路中的数据偏移
公开(公告)号：US07496780B2
公开(公告)日：2009-02-24
申请号：US10364763
申请日：2003-02-11
申请人： Christopher J. Abel , Joseph Anidjar , Abhishek Duggal , Donald R. Laturell
发明人： Christopher J. Abel , Joseph Anidjar , Abhishek Duggal , Donald R. Laturell
IPC分类号： G06F1/12
CPC分类号： H04J3/04 , H04J3/0685 , H04L25/14
摘要： Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.
摘要翻译：具有并行处理通道的信号处理电路具有产生（i）用于驱动信道的高速时钟信号和（ii）用于复位通道处理的同步信号的时钟生成电路。在一个实施例中，信号处理电路具有布置在一个或多个宏小区中的多个复用信道，每个宏小区具有一个或多个信道，以及产生高速PLL时钟信号和同步信号的锁相环（PLL）宏单元的渠道。每个通道具有实现用于驱动多路复用处理的状态机的计数器，其中在接收到同步信号中的每个同步脉冲时状态机被复位到指定状态。

5. 发明申请

US20070194820A1 Phase delay detection apparatus and method with multi-cycle phase range of operation 审中-公开
标题翻译：具有多周期相位范围的相位延迟检测装置及方法
公开(公告)号：US20070194820A1
公开(公告)日：2007-08-23
申请号：US11358260
申请日：2006-02-21
申请人： Abhishek Duggal
发明人： Abhishek Duggal
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A method and apparatus is provided to assure that a delay line control loop will only lock at a desired phase difference—e.g., 360 degrees (and not at the desired phase difference plus a multiple of 360 degrees), between its input and output signals. The phase delay detector of the invention samples multiple signals, from internal stages of the delay line, which are then logically combined to assure that the VCDL will only lock at the desired phase difference.
摘要翻译：提供了一种方法和装置，以确保延迟线控制环路将仅在期望的相位差（例如360度（而不是期望的相位差加上360度的倍数）之间）锁定其输入和输出信号之间。本发明的相位延迟检测器从延迟线的内部级对多个信号进行采样，这些信号然后被逻辑地组合，以确保VCDL将仅锁定在期望的相位差。

6. 发明授权

US08736478B2 Digital-to-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US08736478B2
公开(公告)日：2014-05-27
申请号：US13415898
申请日：2012-03-09
申请人： James A. Bailey , Abhishek Duggal
发明人： James A. Bailey , Abhishek Duggal
IPC分类号： H03M1/66
CPC分类号： H03M1/822 , H03F3/2175 , H03F3/45475 , H03F3/45928 , H03M1/0682
摘要： A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures.
摘要翻译：数模转换器（DAC）具有脉冲宽度编码器，其产生具有与DAC数字输入值成比例的脉冲宽度的充电脉冲。充电脉冲控制在充电脉冲期间选择性地将电流源连接到电容器的充电开关。在充电脉冲结束时，对应于存储在电容器中的电荷的电压形成DAC的模拟输出信号。这样的DAC可以在电容器上配置（1）负增益放大器，以形成负反馈回路，（2）具有多个并联电流源和/或（3）在差分架构中。

7. 发明申请

US20130307518A1 Self-Calibrating Differential Current Circuit 有权
标题翻译：自校准差动电流电路
公开(公告)号：US20130307518A1
公开(公告)日：2013-11-21
申请号：US13472537
申请日：2012-05-16
申请人： Abhishek Duggal
发明人： Abhishek Duggal
IPC分类号： G05F3/02
CPC分类号： G05F3/262
摘要： In one embodiment, a constant-current generator is connected in series with a dependent (e.g., tail) device. A switched capacitor circuit connected to the gate of the dependent device is operated to (i) charge at least one capacitor of the switched capacitor circuit, (ii) use the at least one charged capacitor to adjust the gate voltage of the dependent device to drive the dependent current through the dependent device to be equal to the constant current through the constant-current generator, and (iii) direct the dependent and constant currents through source and sink current nodes.
摘要翻译：在一个实施例中，恒定电流发生器与依赖（例如，尾部）装置串联连接。连接到从属装置的栅极的开关电容器电路被操作为（i）对开关电容器电路的至少一个电容器充电，（ii）使用至少一个充电电容器来调节从属装置的栅极电压以驱动通过相关器件的依赖电流等于通过恒流发生器的恒定电流，以及（iii）通过源极和吸收电流节点引导依赖和恒定的电流。

8. 发明授权

US07366086B2 Crosstalk reduction in a backplane employing low-skew clock distribution 失效
标题翻译：采用低偏移时钟分布的背板中的串扰降低
公开(公告)号：US07366086B2
公开(公告)日：2008-04-29
申请号：US10780945
申请日：2004-02-18
申请人： Christopher J. Abel , Joseph Anidjar , James D. Chlipala , Abhishek Duggal , Donald R. Laturell
发明人： Christopher J. Abel , Joseph Anidjar , James D. Chlipala , Abhishek Duggal , Donald R. Laturell
IPC分类号： H04J1/12
CPC分类号： G06F13/409 , H04B3/32 , H05K1/0216
摘要： A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.
摘要翻译：一种用于背板的系统，其采用i）调整相对高速差分驱动器的发射信号的正负（PN）驱动器偏移以减少远端串扰，ii）高速差分减法电路将至少一个发射信号的增益调整复本与接收信号组合以减少近端串扰，以及iii）锁相环（PLL）同步电路，用于对准一组近端和远端之间的定时事件，结束高速接口。

9. 发明授权

US07330060B2 Method and apparatus for sigma-delta delay control in a delay-locked-loop 失效
标题翻译：延迟锁定环路中Σ-Δ延迟控制的方法和装置
公开(公告)号：US07330060B2
公开(公告)日：2008-02-12
申请号：US11221387
申请日：2005-09-07
申请人： Christopher J. Abel , Abhishek Duggal , Peter C. Metz , Vladimir Sindalovsky
发明人： Christopher J. Abel , Abhishek Duggal , Peter C. Metz , Vladimir Sindalovsky
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/089 , H03L7/093
摘要： Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.
摘要翻译：提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置，其采用延迟线来基于参考信号产生时钟信号。如果时钟信号相对于参考信号具有时间导通，则产生第一值; 并且如果时钟信号相对于参考信号具有时滞，则产生第二值。累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字，其中M小于N.此后，M位数字字可以转换为模拟偏置信号。还原步骤可以由例如Σ-Δ调制器进行。可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

10. 发明申请

US20070052463A1 Method and apparatus for sigma-delta delay control in a Delay-Locked-Loop 失效
标题翻译：延迟锁定环中Σ-Δ延迟控制的方法和装置
公开(公告)号：US20070052463A1
公开(公告)日：2007-03-08
申请号：US11221387
申请日：2005-09-07
申请人： Christopher Abel , Abhishek Duggal , Peter Metz , Vladimir Sindalovsky
发明人： Christopher Abel , Abhishek Duggal , Peter Metz , Vladimir Sindalovsky
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/089 , H03L7/093
摘要： Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.
摘要翻译：提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置，其采用延迟线来基于参考信号产生时钟信号。如果时钟信号相对于参考信号具有时间导通，则产生第一值; 并且如果时钟信号相对于参考信号具有时滞，则产生第二值。累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字，其中M小于N.此后，M位数字字可以转换为模拟偏置信号。还原步骤可以由例如Σ-Δ调制器进行。可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

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