专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07834672B2 Low power charge pump 有权
标题翻译：低功率电荷泵
公开(公告)号：US07834672B2
公开(公告)日：2010-11-16
申请号：US11673569
申请日：2007-02-10
申请人： Christopher G. Arcus , Vincent Tso , James Ho
发明人： Christopher G. Arcus , Vincent Tso , James Ho
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/0802
摘要： A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.
摘要翻译：电荷泵被配置为响应于输入信号来控制输出节点处的电流。基于输入信号生成多个控制信号。控制信号用于控制电荷泵内电流的定时和持续时间，从而降低电荷泵的功耗。基于控制信号，改变电源和输出节点之间的第一路径的电导率和输出节点与地电位之间的第二路径。可选地，电荷泵被设置为锁相环（PLL）的一部分，输入信号由相位/频率检测器产生，并且输出节点处的电流控制振荡器元件。

2. 发明授权

US07132835B1 PLL with built-in filter-capacitor leakage-tester with current pump and comparator 失效
标题翻译： PLL内置滤波电容泄漏测试仪，带电流泵和比较器
公开(公告)号：US07132835B1
公开(公告)日：2006-11-07
申请号：US10248683
申请日：2003-02-07
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： G01R31/08 , G01R31/14
CPC分类号： G01R31/31727 , G01R31/3004 , G11C29/02 , G11C29/023 , G11C29/028 , H03L7/093
摘要： A filter capacitor within a phase-locked loop (PLL) can be tested using a built-in test circuit. The PLL's charge pump is deactivated while a test-current source is activated to supply a test current to the PLL filter capacitor. When the test current is larger than any leakage currents through the capacitor, the capacitor's voltage rises above a reference voltage. A test comparator compares the capacitor's voltage to the reference voltage and signals a good test result when the capacitor's voltage rises above the reference voltage. When leakage current is larger than the test current, the capacitor's voltage cannot rise above the reference voltage and the test comparator signal a leakage failure. The test current source can share a bias voltage with the charge pump and can drive the capacitor to a voltage higher than the charge pump does to increase leakage and stress during testing.
摘要翻译：锁相环（PLL）中的滤波电容可以使用内置测试电路进行测试。当激活测试电流源以向PLL滤波电容提供测试电流时，PLL的电荷泵被禁用。当测试电流大于通过电容器的任何漏电流时，电容器的电压上升到高于参考电压。测试比较器将电容器的电压与参考电压进行比较，当电容器的电压上升到参考电压以上时，会发出良好的测试结果。当漏电流大于测试电流时，电容器的电压不能超过参考电压，并且测试比较器发出泄漏故障。测试电流源可以与电荷泵共享偏置电压，并且可以将电容器驱动到高于电荷泵的电压，以增加测试期间的泄漏和应力。

3. 发明授权

US6124741A Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches 有权
标题翻译：精确的PLL电荷泵具有来自Vds补偿公共开关的匹配上/下电流
公开(公告)号：US6124741A
公开(公告)日：2000-09-26
申请号：US264284
申请日：1999-03-08
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： H03K17/687 , H03L7/089 , H03K3/00
CPC分类号： H03L7/0895 , H03K17/6872
摘要： A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch. The drive transistors are switched on and off by the up and down input pulses by current sources that steer additional current through the supply transistors. The additional current raises the n-channel drive transistor source to turn off the down current. Additional current from a current source also lowers the p-channel drive transistor's source to turn it off. The same polarity and threshold are used for both up and down input pulses, further reducing phase error.
摘要翻译：更精确的电荷泵可以减少PLL中的相位误差。 UP输入脉冲使p沟道驱动晶体管对输出端的滤波电容充电，而下降DN输入脉冲使n沟道驱动晶体管放电输出。驱动晶体管通过电源晶体管连接到电源或接地。电源晶体管在线性区域中被偏置并且不被关断。驱动晶体管的源极总是由电源晶体管驱动，防止浮动源的相位误差。驱动晶体管是共栅开关，其栅极由补偿偏压发生器偏置。通过提供与n沟道驱动晶体管类似的电流变化来补偿具有Vds的p沟道驱动晶体管电流变化。因此，调整偏压以补偿可能导致来自驱动晶体管的上升和下降电流失配的漏极 - 源极电压变化。驱动晶体管由电流源的上下输入脉冲导通和关断，从而引导额外的电流通过电源晶体管。附加电流提高了n沟道驱动晶体管源，以关断下降电流。来自电流源的附加电流也降低了p沟道驱动晶体管的源极，使其截止。相同的极性和阈值用于上下输入脉冲，进一步减少相位误差。

4. 发明授权

US5515012A Very low noise, wide frequency range phase lock loop 失效
标题翻译：噪音极低，频率范围宽的锁相环
公开(公告)号：US5515012A
公开(公告)日：1996-05-07
申请号：US442850
申请日：1995-05-17
申请人： Bharat Bhushan , Christopher G. Arcus , Paul D. Ta
发明人： Bharat Bhushan , Christopher G. Arcus , Paul D. Ta
IPC分类号： H03K3/0231 , H03K3/03 , H03L7/099 , H03B5/04
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/0322
摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.
摘要翻译：锁相环电路的环形多级VCO包括两个或更多个差分放大器级。锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和连接到第二二极管连接的MOS晶体管M2 其漏极端子。差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到锁相环的电压控制输入端。

5. 发明授权

US4890013A Circuit for sensing voltages beyond the supply voltage of the sensing circuit 失效
标题翻译：用于感测电压超过感测电路电源电压的电路
公开(公告)号：US4890013A
公开(公告)日：1989-12-26
申请号：US208310
申请日：1988-06-17
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： G01R19/165 , G01R19/00 , G01R19/10
CPC分类号： G01R19/0038 , G01R19/10
摘要： A voltage sensing circuit wherein voltages that appear at first and second sensing nodes are converted into first and second currents which are proportional to their respective voltages. A comparing circuit compares the first current to the second current and generates a difference current proportional to the difference between the magnitudes of the two currents. A rectifier circuit rectifies the difference current, and the difference current is added to a reference current. The combined current is applied to the first input terminal of a comparator. The second input terminal of the comparator is coupled to a reference voltage, and the comparator indicates when the voltage created from the combined currents exceeds the reference voltage.

6. 发明授权

US4876517A Circuit for sensing FET or IGBT drain current over a wide dynamic range 失效
标题翻译：用于在宽动态范围内感测FET或IGBT漏极电流的电路
公开(公告)号：US4876517A
公开(公告)日：1989-10-24
申请号：US208290
申请日：1988-06-17
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： G01R19/00
CPC分类号： G01R19/0092
摘要： A current sensing circuit includes a pair of power devices connected in parallel. The mirror terminal of the first power device is coupled to a small sense resistance, and the mirror terminal of the second power device is connected to a large sense resistance. Each mirror terminal is coupled to its own comparator. Small currents are sensed by the comparator coupled to the mirror terminal of the first power device, and large currents are sensed by the comparator coupled to the mirror terminal of the second power device. If multiple mirror terminals are not available, a large sense resistance may be connected to the mirror terminal of the power device, and a small sense resistance may be selectively connected in parallel with the large resistance to provide low current-sensing capabilities. Accuracy of the device is enhanced by circuitry which minimizes the effect of integrated impedance variation and a variation in the low sense resistances.
摘要翻译：电流感测电路包括并联连接的一对功率器件。第一功率器件的反射镜端子耦合到小的感测电阻，并且第二功率器件的反射镜端子被连接到大的感测电阻。每个镜像终端耦合到其自己的比较器。小电流被耦合到第一功率器件的反射镜端子的比较器感测，并且由耦合到第二功率器件的反射镜端子的比较器感测到大电流。如果多个反射镜端子不可用，则可以将大的感测电阻连接到功率器件的反射镜端子，并且可以将小的感测电阻与大电阻并联选择性地连接以提供低电流感测能力。通过最小化集成阻抗变化的影响和低感测电阻的变化的电路来增强器件的精度。

7. 发明授权

US06801080B1 CMOS differential input buffer with source-follower input clamps 失效
标题翻译： CMOS差分输入缓冲器，带有源极跟随器输入钳位
公开(公告)号：US06801080B1
公开(公告)日：2004-10-05
申请号：US10249414
申请日：2003-04-07
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： G06G726
CPC分类号： H03K5/08 , H03K5/2481
摘要： A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.
摘要翻译：差分输入缓冲器显示对输入条件（如输入跟踪加载和上游驱动程序特性）的灵敏度降低。可以将输入条件改变为幅度，转换速率和共模偏移的差异。通过输入钳位电路将宽输入电压摆幅钳位到有限的电压范围，输入钳位电路使用源极跟随器驱动输入电压过低时关断的p沟道钳位晶体管。然后分压器将最低电压输入设置到差分级。差分级接收钳位输入，并具有两个尾电流吸收器，以减少对尾电容充电和放电的延迟灵敏度。中间电压被施加到与接收钳位的输入电压的差分晶体管相对的晶体管。通过镜像电流产生尾电流吸收器的偏置电压，并通过从电阻器注入和去除相同的偏置电流来设置栅极电压。

8. 发明授权

US06426662B1 Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays 失效
标题翻译：使用差分分压器和比较器的双环振荡器和延迟线产生多相以匹配延迟
公开(公告)号：US06426662B1
公开(公告)日：2002-07-30
申请号：US09683040
申请日：2001-11-12
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： G06F104
CPC分类号： H03K3/03 , H03K3/0231 , H03K3/0322 , H03K5/133 , H03K2005/00097 , H03L7/0812 , H03L7/0995
摘要： A phase-locked loop (PLL) or a delay-locked loop (DLL) has differential delay stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-phase clocks. To avoid erratic or multiple oscillation and overtones, fewer than eight and preferably four differential delay stages are used. The delay stages are arranged in a twisted-ring with the differential outputs of the last delay stage crossed over and fed back to the differential inputs of the first delay stage. Tail currents of the delay stages can be adjusted by a voltage generated by a PLL loop. The differential toggle flip-flops allow for many taps or clock phases to be generated from the few delay stages.
摘要翻译：锁相环（PLL）或延迟锁定环（DLL）具有差分延迟级，差分输出驱动差分时钟输入到一对差分开关触发器。一个触发器在上升沿改变状态，另一个在延迟阶段的真实输出的下降沿上改变。差分到单端缓冲器将差分触发器输出转换为单端多相时钟。为了避免不稳定或多重振荡和泛音，使用少于八个，优选四个差分延迟级。延迟级布置在扭转环中，最后延迟级的差分输出交叉并反馈到第一延迟级的差分输入。可以通过PLL环路产生的电压来调整延迟级的尾电流。差分触发器允许从几个延迟级产生许多抽头或时钟相位。

9. 发明授权

US06320438B1 Duty-cycle correction driver with dual-filter feedback loop 失效
标题翻译：带双滤波器反馈回路的占空比校正驱动器
公开(公告)号：US06320438B1
公开(公告)日：2001-11-20
申请号：US09641282
申请日：2000-08-17
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies. A control voltage of about Vcc/2 is applied to the source-limiting transistors, causing them to operate in the linear region with limited current. A slow-slew output from the modulator is buffered by a driver. The driver output is filtered by a linear detector with a series resistor and input capacitor. The detector output is compared to a reference voltage of Vcc/2 by an error amp. The error amp generates the control voltage fed back to the modulator. An output capacitor creates a dominant pole with the error amp to ensure stability. A variable-threshold gate can be added between the driver output and the detector to separately adjust the measurement threshold voltage from the reference voltage to the error amp.
摘要翻译：时钟发生器具有占空比校正电路，其将占空比调整到50％。调制器是具有与电源和地面电源串联的额外的源极限制晶体管的反相器。将约Vcc / 2的控制电压施加到源极限制晶体管，使其在有限电流的线性区域中工作。调制器的慢速输出由驱动器缓冲。驱动器输出由具有串联电阻和输入电容的线性检测器滤波。检测器输出通过误差放大器与Vcc / 2的参考电压进行比较。误差放大器产生反馈给调制器的控制电压。输出电容器通过误差放大器产生主导极，以确保稳定性。可以在驱动器输出和检测器之间添加可变阈值门，以将测量阈值电压从参考电压单独调整到误差放大器。

10. 发明授权

US5523723A Low noise low voltage phase lock loop 失效
标题翻译：低噪声低电压锁相环
公开(公告)号：US5523723A
公开(公告)日：1996-06-04
申请号：US443131
申请日：1995-05-17
申请人： Christopher G. Arcus , Bharat Bhushan , Paul D. Ta
发明人： Christopher G. Arcus , Bharat Bhushan , Paul D. Ta
IPC分类号： H03K3/0231 , H03K3/03 , H03L7/099 , H03B5/04
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/0322
摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.
摘要翻译：锁相环电路的环形多级VCO包括两个或更多个差分放大器级。锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和与其连接的二极管连接的MOS晶体管M2 漏极端子。电流源MOS晶体管M8具有连接到第一MOS晶体管M1的漏极的栅极端子，使得晶体管M8镜像晶体管M1的电流。二极管连接的晶体管M9的栅极端子和其漏极端子连接在一起，并且还连接到晶体管M8的漏极端子。差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到晶体管M9的漏极端子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式