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1. 发明申请

US20070189429A1 Low Power Charge Pump 有权
标题翻译：低功率电荷泵
公开(公告)号：US20070189429A1
公开(公告)日：2007-08-16
申请号：US11673569
申请日：2007-02-10
申请人： Christopher Arcus , Vincent Tso , James Ho
发明人： Christopher Arcus , Vincent Tso , James Ho
IPC分类号： H03D3/24
CPC分类号： H03L7/0895 , H03L7/0802
摘要： A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.
摘要翻译：电荷泵被配置为响应于输入信号来控制输出节点处的电流。基于输入信号生成多个控制信号。控制信号用于控制电荷泵内电流的定时和持续时间，从而降低电荷泵的功耗。基于控制信号，改变电源和输出节点之间的第一路径的电导率和输出节点与地电位之间的第二路径。可选地，电荷泵被设置为锁相环（PLL）的一部分，输入信号由相位/频率检测器产生，并且输出节点处的电流控制振荡器元件。

2. 发明授权

US06960942B2 High speed phase selector 有权
标题翻译：高速相位选择器
公开(公告)号：US06960942B2
公开(公告)日：2005-11-01
申请号：US09860723
申请日：2001-05-18
申请人： Bahram Ghaderi , Vincent Tso , Sunil Jaggia , Johnny Lee
发明人： Bahram Ghaderi , Vincent Tso , Sunil Jaggia , Johnny Lee
IPC分类号： G06F1/06 , H03K5/00 , H03K5/135 , H03L7/06 , H03K17/00 , H03K3/00
CPC分类号： G06F1/06 , H03K5/135 , H03K2005/00241 , H03L7/06
摘要： Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.
摘要翻译：用于选择相位的方法和电路，同时避免在相位切换期间输出信号中的毛刺。一种集成电路，具有耦合以接收具有不同相位的相应多个时钟信号的多个输入端子，以及耦合以接收相应的多个相位选择信号的多个控制端子。电路被配置为响应于相位选择信号的第一组合而从多个时钟信号输出第一选定的时钟信号，并且还被配置为响应于第一选择的时钟信号从第一选定的时钟信号切换到第二选择的时钟信号相位选择信号的第二组合。在第二相选择信号接合之后，电路解除第一时钟信号。

3. 发明申请

US20050285637A1 CMOS LvPECL driver with output level control 失效
标题翻译： CMOS LvPECL驱动器，具有输出电平控制
公开(公告)号：US20050285637A1
公开(公告)日：2005-12-29
申请号：US10879475
申请日：2004-06-28
申请人： Timothy Lu , Vincent Tso
发明人： Timothy Lu , Vincent Tso
IPC分类号： H03B1/00 , H03K5/24 , H03K19/0185
CPC分类号： H03K19/018528 , H03K5/2481
摘要： A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.
摘要翻译：差分输出驱动器包括输出块，复制块和反馈控制块。每个输出和复制块还包括前置放大器和源极跟随器级。输出块的前置放大器接收差分输入电压并产生第一差分电压。输出块的源极跟随器级接收第一差分电压并产生差分输出电压。复制块的前置放大器接收第一和第二电源电压并产生第二差分电压。输出块的源极跟随器级接收第二差分电压并产生第三差分电压。反馈控制块接收第三差分电压并产生施加到输出块的差分控制电压。产生的差分输出电压保持在预定义的限制内，例如由LvPECL标准定义的限制。

4. 发明授权

US07834672B2 Low power charge pump 有权
标题翻译：低功率电荷泵
公开(公告)号：US07834672B2
公开(公告)日：2010-11-16
申请号：US11673569
申请日：2007-02-10
申请人： Christopher G. Arcus , Vincent Tso , James Ho
发明人： Christopher G. Arcus , Vincent Tso , James Ho
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/0802
摘要： A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.
摘要翻译：电荷泵被配置为响应于输入信号来控制输出节点处的电流。基于输入信号生成多个控制信号。控制信号用于控制电荷泵内电流的定时和持续时间，从而降低电荷泵的功耗。基于控制信号，改变电源和输出节点之间的第一路径的电导率和输出节点与地电位之间的第二路径。可选地，电荷泵被设置为锁相环（PLL）的一部分，输入信号由相位/频率检测器产生，并且输出节点处的电流控制振荡器元件。

5. 发明申请

US20060238263A1 Detection Of A Closed Loop Voltage 审中-公开
标题翻译：检测闭环电压
公开(公告)号：US20060238263A1
公开(公告)日：2006-10-26
申请号：US11428325
申请日：2006-06-30
申请人： Vincent Tso , James Ho
发明人： Vincent Tso , James Ho
IPC分类号： H03L7/00
CPC分类号： H03K5/2481 , H03L7/10
摘要： To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.
摘要翻译：为了检测闭环电压是否超出范围，电压检测器包括分别向第一和第二高阻抗节点传送第一和第二电流的第一和第二晶体管。电压检测器还包括分别从第一和第二节点划分第三和第四电流的第三和第四晶体管。第一和第二电流是流过电流 - 电流转换器的电流源的电流的缩放副本，其将闭环电压转换成电流并将第一电压提供给第一和第二晶体管。第三和第四电流是流过电压 - 电流转换器的电流镜的不同电流的缩放副本，并且向第三和第四晶体管提供第二电压。

6. 发明申请

US20060066359A1 Detection of a closed loop voltage 失效
公开(公告)号：US20060066359A1
公开(公告)日：2006-03-30
申请号：US10956357
申请日：2004-09-30
申请人： Vincent Tso , James Ho
发明人： Vincent Tso , James Ho
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03L7/10
摘要： To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.

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