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1. 发明申请

US20120168833A1 FORMATION OF FINFET GATE SPACER 有权
标题翻译：形成FINFET GATE SPACER
公开(公告)号：US20120168833A1
公开(公告)日：2012-07-05
申请号：US13419508
申请日：2012-03-14
申请人： Douglas BONSER , Catherine B. LABELLE
发明人： Douglas BONSER , Catherine B. LABELLE
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.
摘要翻译：在具有延伸到翅片的高度的第一材料的底部的FinFETS中形成栅极间隔物，以及在鳍片上方延伸的第二材料的顶部。一个实施例包括在衬底上形成翅片结构，翅片结构具有高度并具有顶表面和侧表面，在顶表面和侧表面的一部分上形成基本上垂直于鳍结构的栅极，例如在中心在栅极上形成平坦化层，鳍结构和衬底，将平坦化层从衬底，栅极和鳍结构移除到翅片结构的高度，并且在翅片结构上和在翅片结构上形成间隔物平坦化层，邻近门。

2. 发明申请

US20110198673A1 FORMATION OF FINFET GATE SPACER 有权
标题翻译：形成FINFET GATE SPACER
公开(公告)号：US20110198673A1
公开(公告)日：2011-08-18
申请号：US12707291
申请日：2010-02-17
申请人： Douglas Bonser , Catherine B. Labelle
发明人： Douglas Bonser , Catherine B. Labelle
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/66795 , H01L29/785
摘要： Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.
摘要翻译：在具有延伸到翅片的高度的第一材料的底部的FinFETS中形成栅极间隔物，以及在鳍片上方延伸的第二材料的顶部。一个实施例包括在衬底上形成翅片结构，翅片结构具有高度并具有顶表面和侧表面，在顶表面和侧表面的一部分上形成基本上垂直于鳍结构的栅极，例如在中心在栅极上形成平坦化层，鳍结构和衬底，将平坦化层从衬底，栅极和鳍结构移除到翅片结构的高度，并且在翅片结构上和在翅片结构上形成间隔物平坦化层，邻近门。

3. 发明申请

US20100267237A1 METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING ASHABLE SACRIFICIAL MANDRELS 审中-公开
标题翻译：使用可靠的SACRIFICIC MANDRELS制造FINFET半导体器件的方法
公开(公告)号：US20100267237A1
公开(公告)日：2010-10-21
申请号：US12426824
申请日：2009-04-20
申请人： Douglas J. Bonser , Frank S. Johnson , Catherine B. Labelle
发明人： Douglas J. Bonser , Frank S. Johnson , Catherine B. Labelle
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L29/66795
摘要： Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel. The sacrificial mandrel is removed using an ashing process, and the substrate is etched using the sidewall spacers as an etch mask after removal of the sacrificial mandrel.
摘要翻译：提供了用于在半导体衬底上和半导体衬底中制造半导体器件的方法。根据本发明的示例性实施例，一种方法包括形成覆盖在基底上的牺牲心轴，牺牲心轴具有侧壁。侧壁间隔件邻近牺牲心轴的侧壁形成。使用灰化处理去除牺牲心轴，并且在去除牺牲心轴之后，使用侧壁间隔物作为蚀刻掩模蚀刻衬底。

4. 发明授权

US06746973B1 Effect of substrate surface treatment on 193 NM resist processing 失效
标题翻译：衬底表面处理对193 NM抗蚀剂加工的影响
公开(公告)号：US06746973B1
公开(公告)日：2004-06-08
申请号：US10212985
申请日：2002-08-05
申请人： Catherine B. Labelle , Ernesto Gallardo , Ramkumar Subramanian , Jacques Bertrand
发明人： Catherine B. Labelle , Ernesto Gallardo , Ramkumar Subramanian , Jacques Bertrand
IPC分类号： H01L21302
CPC分类号： G03F7/16 , G03F7/091 , H01L21/3105 , H01L21/31144
摘要： One aspect of the present invention relates to a system and method for mitigating surface abnormalities on a semiconductor structure. The method involves exposing the layer to a first plasma treatment in order to mitigate surface interactions between the layer and a subsequently formed photoresist without substantially etching the layer, the first plasma comprising oxygen and nitrogen; forming a patterned photoresist over the treated layer, the patterned photoresist being formed using 193 nm or lower radiation; and etching the treated layer through openings of the patterned photoresist. The system and method also includes a monitor processor for determining whether the plasma treatment has been administered and for adjusting the plasma treatment components. The monitor processor transmits a pulse, receives a reflected pulse response and analyzes the response. An optional second plasma treatment comprising nitrogen and hydrogen may be administered after the first plasma treatment but before forming the photoresist.
摘要翻译：本发明的一个方面涉及一种用于减轻半导体结构上的表面异常的系统和方法。该方法包括将层暴露于第一等离子体处理，以便减轻层与随后形成的光致抗蚀剂之间的表面相互作用，而基本上不蚀刻该层，第一等离子体包含氧和氮; 在处理的层上形成图案化的光致抗蚀剂，使用193nm或更低的辐射形成图案化的光致抗蚀剂; 并通过图案化光致抗蚀剂的开口蚀刻处理层。该系统和方法还包括用于确定等离子体处理是否已被施用并用于调整等离子体处理组件的监视器处理器。监视器处理器发送脉冲，接收反射的脉冲响应并分析响应。包括氮和氢的任选的第二等离子体处理可以在第一等离子体处理之后但在形成光致抗蚀剂之前施用。

5. 发明授权

US06982043B1 Scatterometry with grating to observe resist removal rate during etch 有权
标题翻译：用光栅进行散射测量以观察蚀刻期间的抗蚀剂去除率
公开(公告)号：US06982043B1
公开(公告)日：2006-01-03
申请号：US10382181
申请日：2003-03-05
申请人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
发明人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
IPC分类号： B44C1/22
CPC分类号： H01L22/12 , H01L22/26
摘要： Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.
摘要翻译：公开了用于监测经历蚀刻工艺的图案化光致抗蚀剂包覆晶片结构的系统和方法。该系统包括半导体晶片结构，其包括衬底，覆盖衬底的一个或多个中间层和覆盖中间层的第一图案化光致抗蚀剂层，半导体晶片结构通过光致抗蚀剂层中的一个或多个开口进行蚀刻; 晶片蚀刻光刻胶监测系统被编程为随着蚀刻工艺的进行获得与光致抗蚀剂层有关的数据; 与晶片结构对准并与监视系统结合使用的图案特定光栅，光栅具有与第一图案化光致抗蚀剂层相同的间距和临界尺寸中的至少一个; 以及晶片处理控制器，可操作地连接到所述监控系统并且适于从所述监控系统接收数据，以便确定随后的晶片清洁过程的调整。

6. 发明授权

US08525234B2 Formation of FinFET gate spacer 有权
标题翻译： FinFET栅极隔离层的形成
公开(公告)号：US08525234B2
公开(公告)日：2013-09-03
申请号：US13419508
申请日：2012-03-14
申请人： Douglas Bonser , Catherine B. Labelle
发明人： Douglas Bonser , Catherine B. Labelle
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L29/785
摘要： Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.
摘要翻译：在具有延伸到翅片的高度的第一材料的底部的FinFETS中形成栅极间隔物，以及在鳍片上方延伸的第二材料的顶部。一个实施例包括在衬底上形成翅片结构，翅片结构具有高度并具有顶表面和侧表面，在顶表面和侧表面的一部分上形成基本上垂直于鳍结构的栅极，例如在中心在栅极上形成平坦化层，鳍结构和衬底，将平坦化层从衬底，栅极和鳍结构移除到翅片结构的高度，并且在翅片结构上和在翅片结构上形成间隔物平坦化层，邻近门。

7. 发明授权

US08174055B2 Formation of FinFET gate spacer 有权
标题翻译： FinFET栅极隔离层的形成
公开(公告)号：US08174055B2
公开(公告)日：2012-05-08
申请号：US12707291
申请日：2010-02-17
申请人： Douglas Bonser , Catherine B. Labelle
发明人： Douglas Bonser , Catherine B. Labelle
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L29/785
摘要： Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.
摘要翻译：在具有延伸到翅片的高度的第一材料的底部的FinFETS中形成栅极间隔物，以及在鳍片上方延伸的第二材料的顶部。一个实施例包括在衬底上形成翅片结构，翅片结构具有高度并具有顶表面和侧表面，在顶表面和侧表面的一部分上形成基本上垂直于鳍结构的栅极，例如在中心在栅极上形成平坦化层，鳍结构和衬底，将平坦化层从衬底，栅极和鳍结构移除到翅片结构的高度，并且在翅片结构上和在翅片结构上形成间隔物平坦化层，邻近门。

8. 发明授权

US06793765B1 Situ monitoring of microloading using scatterometry with variable pitch gratings 失效
标题翻译：使用具有可变间距光栅的散射法对微载荷进行现场监测
公开(公告)号：US06793765B1
公开(公告)日：2004-09-21
申请号：US10230739
申请日：2002-08-29
申请人： Catherine B. Labelle , Bhanwar Singh , Bharath Rangarajan
发明人： Catherine B. Labelle , Bhanwar Singh , Bharath Rangarajan
IPC分类号： H05H100
CPC分类号： H01L22/20 , H01J37/32935 , H01J37/3299 , H01L21/3065
摘要： One aspect of the present invention relates to a system for determining and controlling a microloading effect in order to achieve desired feature depth on a wafer. The system includes a semiconductor structure having one or more layers formed over a substrate, a fabrication process assembly for forming features on the semiconductor structure, a microloading characterization system for monitoring the fabrication process, measuring feature depth, and for processing the measurements in order to ascertain the microloading effect, a detection apparatus operatively coupled to the microloading characterization system to facilitate monitoring the fabrication process and measuring feature depth, and a control system for regulating the fabrication process based on the output from the microloading characterization system. Thus, forming features having a first density and features having a second density on the same layer may be formed using one photomask since fabrication parameters can be adjusted based on the determined microloading effect.
摘要翻译：本发明的一个方面涉及一种用于确定和控制微加载效应以便在晶片上实现期望的特征深度的系统。该系统包括在衬底上形成一层或多层的半导体结构，用于在半导体结构上形成特征的制造工艺组件，用于监测制造工艺，测量特征深度和用于处理测量的微加载表征系统，确定微载荷效应，可操作地耦合到微加载表征系统以便于监测制造过程和测量特征深度的检测装置，以及用于基于来自微载体表征系统的输出来调节制造过程的控制系统。因此，可以使用一个光掩模形成具有第一密度的成形特征和在同一层上具有第二密度的特征，因为可以基于确定的微加载效应来调整制造参数。

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