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1. 发明申请

US20110285575A1 INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE 有权
标题翻译：包含用于控制频率源的频率发生电路的集成电路
公开(公告)号：US20110285575A1
公开(公告)日：2011-11-24
申请号：US13145122
申请日：2009-02-13
申请人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
发明人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
IPC分类号： G01S13/02
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
摘要翻译：集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

2. 发明授权

US08654006B2 Integrated circuit comprising frequency generation circuitry for controlling a frequency source 有权
标题翻译：集成电路，包括用于控制频率源的频率产生电路
公开(公告)号：US08654006B2
公开(公告)日：2014-02-18
申请号：US13145122
申请日：2009-02-13
申请人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
发明人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
IPC分类号： G01S7/28
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
摘要翻译：集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

3. 发明申请

US20130187719A1 PLL SYSTEM AND METHOD FOR CONTROLLING A GAIN OF A VCO CIRCUIT 有权
标题翻译：用于控制VCO电路的增益的PLL系统和方法
公开(公告)号：US20130187719A1
公开(公告)日：2013-07-25
申请号：US12936214
申请日：2008-04-18
申请人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
发明人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
IPC分类号： H03L7/16
CPC分类号： H03L7/16 , H03B5/1228 , H03B2201/0208 , H03L7/099 , H03L7/113 , H03L7/18
摘要： A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
摘要翻译：一种锁相环系统，包括：压控振荡器电路，包括第一多个可切换变容二极管，用于选择VCO的频带，其具有随频带变化的增益;以及第二多个可切换变容二极管，用于改变在所选频段的增益。 PLL系统具有PLL反馈电路，其包括用于将反馈电路切换到开环状态的开关装置，其中多个预定调谐电压可以施加到VCO; 用于测量合成VCO频率的频率测量装置; 以及控制单元，用于确定相对于合成频率和调谐电压的增益。

4. 发明授权

US08912857B2 PLL system and method for controlling a gain of a VCO circuit 有权
标题翻译： PLL系统和控制VCO电路增益的方法
公开(公告)号：US08912857B2
公开(公告)日：2014-12-16
申请号：US12936214
申请日：2008-04-18
申请人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
发明人： Hugues Beaulaton , Thierry Cassagnes , Stéphane Colomines , Didier Salle
IPC分类号： H03B5/12 , H03L7/16 , H03L7/099 , H03L7/113 , H03L7/18
CPC分类号： H03L7/16 , H03B5/1228 , H03B2201/0208 , H03L7/099 , H03L7/113 , H03L7/18
摘要： A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
摘要翻译：一种锁相环系统，包括：压控振荡器电路，包括第一多个可切换变容二极管，用于选择VCO的频带，其具有随频带变化的增益;以及第二多个可切换变容二极管，用于改变在所选频段的增益。 PLL系统具有PLL反馈电路，其包括用于将反馈电路切换到开环状态的开关装置，其中多个预定调谐电压可以施加到VCO; 用于测量合成VCO频率的频率测量装置; 以及控制单元，用于确定相对于合成频率和调谐电压的增益。

5. 发明授权

US07880516B2 Method for noise reduction in a phase locked loop and a device having noise reduction capabilities 有权
标题翻译：锁相环中的降噪方法和具有降噪能力的装置
公开(公告)号：US07880516B2
公开(公告)日：2011-02-01
申请号：US11910062
申请日：2005-03-31
申请人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
发明人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/081 , H03L7/1976
摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.
摘要翻译：一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号和分频信号之间的差。一种包含锁相环的装置。锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

6. 发明申请

US20080265958A1 Method for Noise Reduction in a Phase Locked Loop and a Device Having Noise Reduction Capabilities 有权
标题翻译：一种锁相环路降噪方法及具有降噪能力的装置
公开(公告)号：US20080265958A1
公开(公告)日：2008-10-30
申请号：US11910062
申请日：2005-03-31
申请人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
发明人： Hugues Beaulaton , Stephane Colomines , Philippe Gorisse
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/081 , H03L7/1976
摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.
摘要翻译：一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号与分频信号之间的差。一种包含锁相环的装置。锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

7. 发明申请

US20160290804A1 IN-BAND BEATING REMOVAL FOR A MEMS GYROSCOPE 审中-公开
标题翻译：用于MEMS陀螺仪的带内去除
公开(公告)号：US20160290804A1
公开(公告)日：2016-10-06
申请号：US15035869
申请日：2013-11-22
申请人： Thierry CASSAGNES , Hugues BEAULATON , Laurent CORNIBERT , Yean Ling TEO
发明人： Thierry Cassagnes , Hugues Beaulaton , Laurent Cornibert , Yean Ling Teo
IPC分类号： G01C19/5726 , H04L7/033 , G06F1/08
CPC分类号： G01C19/5726 , G01C19/04 , G06F1/08 , G06F1/1694 , H04L7/033 , H04L7/06
摘要： A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS gyroscope (VMEMS). The circuitry comprises drive circuitry (DRIVE) arranged to drive, when the circuitry is connected, the vibration MEMS gyroscope (VMEMS) and a measurement unit (DMU) which provides a drive measurement voltage signal (DMV) forming a measure of a displacement of a mass along a drive axis. A sense circuitry (SENSE) is arranged to process a sense measurement signal of the vibration MEMS gyroscope (VMEMS) forming a measure for a displacement of the mass along a sense axis. A digital sample clock generator (SCG) is arranged to generate a sample clock signal (SCLK) from an input signal (FDxy) derivable from a drive measurement voltage signal (DMV). The sample clock generator (SCG) comprises an oscillator (HFOSC) arranged to generate a master clock (MOSC), and a counter unit (OSCCNTR) arranged to count master clock periods during one period of the input signal. The clock generator also comprises a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, and to compare the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit). A frequency shifter (FSH) will trigger the oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).
摘要翻译：振动陀螺仪电路（VCIRC）可连接到振动MEMS陀螺仪（VMEMS）。电路包括驱动电路（DRIVE），驱动电路（DRIVE）被布置成在电路连接时驱动振动MEMS陀螺仪（VMEMS）和测量单元（DMU），其提供驱动测量电压信号（DMV），其形成一个沿驱动轴的质量。感测电路（SENSE）被布置为处理振动MEMS陀螺仪（VMEMS）的感测测量信号，其形成沿着感测轴的质量位移的测量。数字采样时钟发生器（SCG）被布置成从可从驱动测量电压信号（DMV）导出的输入信号（FDxy）产生采样时钟信号（SCLK）。采样时钟发生器（SCG）包括布置成产生主时钟（MOSC）的振荡器（HFOSC）和被配置为在输入信号的一个周期期间对主时钟周期进行计数的计数器单元（OSCCNTR）。时钟发生器还包括一个数字计数监视器（NCM），用于确定在数量保持不变的多少个输入信号周期内，以及将常数周期数（Ncp）与临界数量的恒定周期（Ncp_crit）进行比较。每当数字监视（NCM）确定恒定周期数（Ncp）超过常数周期（Ncp_crit）的临界数时，移频器（FSH）将触发振荡器来移动主时钟频率。

8. 发明授权

US07605652B2 Loop gain equalizer for RF power amplifier 有权
标题翻译： RF功率放大器的环路增益均衡器
公开(公告)号：US07605652B2
公开(公告)日：2009-10-20
申请号：US12063012
申请日：2005-08-05
申请人： Hugues Beaulaton , Gerald Haennig , Didier Salle
发明人： Hugues Beaulaton , Gerald Haennig , Didier Salle
IPC分类号： H03G3/20
CPC分类号： H03F1/02 , H03F1/0272 , H03F2200/105 , H03F2200/78
摘要： The output power of an RF power amplifier is controlled using a feedback loop including a differential integrator for controlling the amplifier's bias voltage. The gain of integration in the differential integrator is varied so as to compensate for variations in the derivative of the power amplifier output power versus the bias voltage.
摘要翻译：使用包括用于控制放大器的偏置电压的差分积分器的反馈回路来控制RF功率放大器的输出功率。差分积分器的积分增益是变化的，以便补偿功率放大器输出功率相对于偏置电压的导数的变化。

9. 发明授权

US10119822B2 In-band beating removal for a MEMS gyroscope 有权
公开(公告)号：US10119822B2
公开(公告)日：2018-11-06
申请号：US15035869
申请日：2013-11-22
申请人： Thierry Cassagnes , Hugues Beaulaton , Laurent Cornibert , Yean Ling Teo
发明人： Thierry Cassagnes , Hugues Beaulaton , Laurent Cornibert , Yean Ling Teo
IPC分类号： G01C19/5726 , G01C19/04 , G01F1/08 , H04L7/033 , H04L7/06 , G06F1/08 , G06F1/16
摘要： Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.

10. 发明授权

US09644965B2 System comprising a mechanical resonator and method therefor 有权
公开(公告)号：US09644965B2
公开(公告)日：2017-05-09
申请号：US14642202
申请日：2015-03-09
申请人： Hugues Beaulaton , Thierry Cassagnes , Laurent Cornibert , Volker Wahl
发明人： Hugues Beaulaton , Thierry Cassagnes , Laurent Cornibert , Volker Wahl
IPC分类号： G01C19/5776 , G01C19/5726
CPC分类号： G01C19/5776 , G01C19/5726 , H03B2200/0094
摘要： A system comprises a mechanical resonator; an analog circuit operably coupled to the mechanical resonator; the analog circuit arranged to receive a mechanical resonator measurement signal and to output a mechanical resonator actuation signal to the mechanical resonator; and a digital actuator operably coupled to the analog circuit and configured to provide a frequency sweep of signals to the analog circuit that induces movement of the mechanical resonator.

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