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1. 发明申请

US20050170660A1 Method of depositing a layer of a material on a substrate 失效
标题翻译：在衬底上沉积材料层的方法
公开(公告)号：US20050170660A1
公开(公告)日：2005-08-04
申请号：US11009825
申请日：2004-12-10
申请人： Christoph Schwan , Thomas Feudel , Thorsten Kammler
发明人： Christoph Schwan , Thomas Feudel , Thorsten Kammler
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L29/417 , H01L21/00 , H01L21/8234
CPC分类号： H01L29/66628 , H01L21/28123 , H01L21/28247 , H01L21/31116 , H01L21/32137 , H01L29/41775 , H01L29/41783 , H01L29/6656
摘要： The present invention makes it possible to precisely deposit a material adjacent a feature on a substrate. A layer of the material is deposited on the substrate. The layer is planarized and exposed to an etchant. The etchant is adapted to selectively remove the material. The exposing of the layer to the etchant is stopped prior to a complete removal of the layer.
摘要翻译：本发明使得可以将与特征相邻的材料精确地沉积在基底上。材料层沉积在基底上。该层被平坦化并暴露于蚀刻剂。蚀刻剂适于选择性地去除材料。在完全除去层之前，停止将该层暴露于蚀刻剂。

2. 发明授权

US07338872B2 Method of depositing a layer of a material on a substrate 失效
标题翻译：在衬底上沉积材料层的方法
公开(公告)号：US07338872B2
公开(公告)日：2008-03-04
申请号：US11009825
申请日：2004-12-10
申请人： Christoph Schwan , Thomas Feudel , Thorsten Kammler
发明人： Christoph Schwan , Thomas Feudel , Thorsten Kammler
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/28123 , H01L21/28247 , H01L21/31116 , H01L21/32137 , H01L29/41775 , H01L29/41783 , H01L29/6656
摘要： The present invention makes it possible to precisely deposit a material adjacent a feature on a substrate. A layer of the material is deposited on the substrate. The layer is planarized and exposed to an etchant. The etchant is adapted to selectively remove the material. The exposing of the layer to the etchant is stopped prior to a complete removal of the layer.
摘要翻译：本发明使得可以将与特征相邻的材料精确地沉积在基底上。材料层沉积在基底上。该层被平坦化并暴露于蚀刻剂。蚀刻剂适于选择性地去除材料。在完全除去层之前，停止将该层暴露于蚀刻剂。

3. 发明授权

US07192881B2 Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity 有权
标题翻译：通过增加蚀刻选择性来形成用于电路元件的侧壁间隔元件的方法
公开(公告)号：US07192881B2
公开(公告)日：2007-03-20
申请号：US10987466
申请日：2004-11-12
申请人： Thorsten Kammler , Karsten Wieczorek , Christoph Schwan
发明人： Thorsten Kammler , Karsten Wieczorek , Christoph Schwan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/6659 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/02318 , H01L21/31116 , H01L21/31612 , H01L29/665 , H01L29/6656
摘要： By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.
摘要翻译：通过在图案化氮化硅间隔层之前热处理二氧化硅衬垫，二氧化硅相对于氮化硅的蚀刻选择性增加，从而减少或消除了通过二氧化硅层的点蚀问题。这允许进一步缩放器件，其中需要非常薄的二氧化硅衬垫以获得漏极和源极区域中的掺杂剂分布图的精确横向图案化。

4. 发明授权

US07005358B2 Technique for forming recessed sidewall spacers for a polysilicon line 有权
标题翻译：用于形成多晶硅线路的凹陷侧壁间隔物的技术
公开(公告)号：US07005358B2
公开(公告)日：2006-02-28
申请号：US10786401
申请日：2004-02-25
申请人： Thorsten Kammler , Katja Huy , Christoph Schwan
发明人： Thorsten Kammler , Katja Huy , Christoph Schwan
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.
摘要翻译：在形成复杂的场效应晶体管的双间隔或多间隔方法中，栅极电极的上侧壁部分可以在外间隔元件的凹陷期间被有效地暴露，因为外间隔件基本上由相同的材料组成作为衬垫材料。因此，用于凹陷外侧壁间隔件的各向异性蚀刻工艺还有效地去除了上侧壁部分上的衬垫残留物，并为难熔金属提供了增加的扩散路径。此外，可以通过相应地控制用于去除氧化物残余物的各向同性蚀刻工艺来增加漏极和源极区域上的硅化物区域的横向延伸。

5. 发明申请

US20050026380A1 Technique for forming recessed sidewall spacers for a polysilicon line 有权
标题翻译：用于形成多晶硅线路的凹陷侧壁间隔物的技术
公开(公告)号：US20050026380A1
公开(公告)日：2005-02-03
申请号：US10786401
申请日：2004-02-25
申请人： Thorsten Kammler , Katja Huy , Christoph Schwan
发明人： Thorsten Kammler , Katja Huy , Christoph Schwan
IPC分类号： H01L21/335 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.
摘要翻译：在形成复杂的场效应晶体管的双间隔或多间隔方法中，栅极电极的上侧壁部分可以在外间隔元件的凹陷期间被有效地暴露，因为外间隔件基本上由相同的材料组成作为衬垫材料。因此，用于凹陷外侧壁间隔件的各向异性蚀刻工艺还有效地去除了上侧壁部分上的衬垫残留物，并为难熔金属提供了增加的扩散路径。此外，可以通过相应地控制用于去除氧化物残余物的各向同性蚀刻工艺来增加漏极和源极区域上的硅化物区域的横向延伸。

6. 发明申请

US20050118769A1 Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity 有权
标题翻译：通过增加蚀刻选择性来形成用于电路元件的侧壁间隔元件的方法
公开(公告)号：US20050118769A1
公开(公告)日：2005-06-02
申请号：US10987466
申请日：2004-11-12
申请人： Thorsten Kammler , Karsten Wieczorek , Christoph Schwan
发明人： Thorsten Kammler , Karsten Wieczorek , Christoph Schwan
IPC分类号： H01L21/311 , H01L21/316 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/02318 , H01L21/31116 , H01L21/31612 , H01L29/665 , H01L29/6656
摘要： By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.
摘要翻译：通过在图案化氮化硅间隔层之前热处理二氧化硅衬垫，二氧化硅相对于氮化硅的蚀刻选择性增加，从而减少或消除了通过二氧化硅层的点蚀问题。这允许进一步缩放器件，其中需要非常薄的二氧化硅衬垫以获得漏极和源极区域中的掺杂剂分布图的精确横向图案化。

7. 发明申请

US20050233532A1 Method of forming sidewall spacers 审中-公开
标题翻译：形成侧墙的方法
公开(公告)号：US20050233532A1
公开(公告)日：2005-10-20
申请号：US11039084
申请日：2005-01-19
申请人： Markus Lenski , Falk Graetsch , Carsten Reichel , Christoph Schwan , Helmut Bierstedt , Thorsten Kammler , Martin Mazur
发明人： Markus Lenski , Falk Graetsch , Carsten Reichel , Christoph Schwan , Helmut Bierstedt , Thorsten Kammler , Martin Mazur
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/337 , H01L29/45 , H01L29/74 , H01L29/78 , H01L31/111
CPC分类号： H01L21/31144 , H01L21/32139 , H01L29/6659 , H01L29/7833
摘要： The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers are substantially not affected by the etchant. Thus, the one or more protective layers protect the feature from being exposed to the etchant.
摘要翻译：本发明允许在衬底上形成与特征相邻的侧壁间隔件，而不会有不希望的特征侵蚀。该特征被一个或多个保护层覆盖。隔离材料层沉积在特征上并各向异性地蚀刻。在各向异性蚀刻中使用的蚀刻剂适于选择性地去除间隔物材料，而一个或多个保护层基本上不受蚀刻剂的影响。因此，一个或多个保护层保护特征不暴露于蚀刻剂。

8. 发明授权

US08564089B2 Electronic fuse structure formed using a metal gate electrode material stack configuration 有权
标题翻译：使用金属栅电极材料堆叠配置形成的电子熔丝结构
公开(公告)号：US08564089B2
公开(公告)日：2013-10-22
申请号：US12941595
申请日：2010-11-08
申请人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
发明人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.
摘要翻译：在复杂的半导体器件中，可以通过使用铝材料作为用于在电子熔丝中诱导电迁移的有效金属的替代栅极方法来提供电子熔丝。电子熔断器可以形成在隔离结构上，从而提供电子熔断器与半导体材料和衬底材料的有效的热解耦，从而使得能够以大体积配置提供有效的电子保险丝，同时避免将熔丝引入金属化系统。

9. 发明申请

US20070001203A1 SEMICONDUCTOR DEVICE INCLUDING A VERTICAL DECOUPLING CAPACITOR 有权
标题翻译：半导体器件，包括垂直去耦电容器
公开(公告)号：US20070001203A1
公开(公告)日：2007-01-04
申请号：US11379605
申请日：2006-04-21
申请人： MATTHIAS LEHR , Kai Frohberg , Christoph Schwan
发明人： MATTHIAS LEHR , Kai Frohberg , Christoph Schwan
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/0629
摘要： A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also provides enhanced pattern uniformity during the highly critical gate patterning process.
摘要翻译：提供了用于去耦电容器的垂直或三维非平面配置，这大大减少了高电荷载流子存储容量的电容器所需的管芯面积。去耦电容器的非平面配置还在高度关键的栅极图案化工艺期间提供增强的图案均匀性。

10. 发明授权

US06696334B1 Method for formation of a differential offset spacer 有权
标题翻译：形成差动偏移间隔物的方法
公开(公告)号：US06696334B1
公开(公告)日：2004-02-24
申请号：US10260485
申请日：2002-09-30
申请人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
发明人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.
摘要翻译：提出了一种适用于掺入高级CMOS技术设备的制造工艺中的差分偏移间隔物形成方法。该方法包括形成覆盖多个栅极结构的第一绝缘层，然后形成覆盖第一绝缘层的第二绝缘层。形成掩模以暴露覆盖第一晶体管类型的栅极结构的第二绝缘层的第一部分，并且保护覆盖第二晶体管类型的晶体管的栅极结构的第二绝缘层的第二部分。然后蚀刻覆盖第一类型的栅极结构的第二绝缘层的暴露的第一部分。在蚀刻之后，去除掩模，并且蚀刻第二绝缘层和第一绝缘层的暴露的第二部分以形成邻接栅极结构的差分间隔物。端点用于停止间隔物蚀刻工艺。

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