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1. 发明授权

US07005355B2 Method for fabricating semiconductor memories with charge trapping memory cells 失效
标题翻译：用电荷俘获存储单元制造半导体存储器的方法
公开(公告)号：US07005355B2
公开(公告)日：2006-02-28
申请号：US10735411
申请日：2003-12-12
申请人： Christoph Kleint , Christoph Ludwig , Joachim Deppe , Jens-Uwe Sachse
发明人： Christoph Kleint , Christoph Ludwig , Joachim Deppe , Jens-Uwe Sachse
IPC分类号： H01L21/74 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.
摘要翻译：一种制造半导体器件的方法包括：在半导体本体上形成存储层。存储层包括第一边界层，中间存储层和第二边界层。存储层被图案化，使得存储层中的至少一些从半导体主体的第一部分上方移除，并且存储层中的一些从半导体本体的第二部分上移除。半导体本体的第一部分被掺杂，半导体本体的第二部分被蚀刻。

2. 发明授权

US07015095B2 Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate 失效
标题翻译：一种制造具有电荷捕获存储单元和半导体衬底的半导体存储器的方法
公开(公告)号：US07015095B2
公开(公告)日：2006-03-21
申请号：US10856414
申请日：2004-05-27
申请人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
发明人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.
摘要翻译：导电材料被引入到字线（2）之间的间隙中，并且使用掩模（6）部分地移除，使得导电材料的残留部分（7）在每种情况下填充相关间隙的一部分并产生与源/漏区（15）的电接触。对于导电材料的另外部分，可以形成用于制造工艺的对准标记。

3. 发明申请

US20060065922A1 Semiconductor memory with vertical charge-trapping memory cells and fabrication 审中-公开
标题翻译：具有垂直电荷捕获存储单元和制造的半导体存储器
公开(公告)号：US20060065922A1
公开(公告)日：2006-03-30
申请号：US11272637
申请日：2005-11-14
申请人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
发明人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L29/40117 , H01L29/66833
摘要： A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.
摘要翻译：半导体器件通过在半导体本体中形成多个沟槽而形成。沟槽在有源沟槽和隔离沟槽之间交替，隔离沟槽比有源沟槽更深。半导体本体被掺杂，使得与每个有源沟槽相邻的半导体本体的顶表面和每个有源沟槽的底板被掺杂。在每个有源沟槽中形成存储单元元件。存储单元部件包括设置在栅电极和沟槽的侧壁之间的栅电极和电荷捕获层。电荷捕获层包括设置在第一和第二限制层之间的存储层。位线形成在半导体主体上并与邻近有源沟槽的半导体本体的顶表面相邻的电耦合掺杂区。位线触点耦合到位线。

4. 发明授权

US06992348B2 Semiconductor memory with vertical charge-trapping memory cells and fabrication 失效
标题翻译：具有垂直电荷捕获存储单元和制造的半导体存储器
公开(公告)号：US06992348B2
公开(公告)日：2006-01-31
申请号：US10741970
申请日：2003-12-19
申请人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
发明人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L29/66833
摘要： Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.
摘要翻译：在存储单元场之外，在顶位线上提供位线触点，并且在下位线上提供额外的位线触点，并且各自以导电方式连接到为布线提供的金属化层。用于高位线的位线触点和用于低位线的附加位线触点形成在存储器单元场的相对侧上，并且隔离沟槽的部分存在于附加位线触点之间。

5. 发明申请

US20060205148A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060205148A1
公开(公告)日：2006-09-14
申请号：US11078647
申请日：2005-03-11
申请人： Joachim Deppe , Mathias Krause , Christoph Kleint , Christoph Ludwig , Jens-Uwe Sachse , Gunther Wein
发明人： Joachim Deppe , Mathias Krause , Christoph Kleint , Christoph Ludwig , Jens-Uwe Sachse , Gunther Wein
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8238
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trappinig element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5). The nitride spacers (10) cover the electrically insulating elements (21) and are arranged on opposing sidewalls (25) of the gate stack (20) and on the electrically insulating elements (21).
摘要翻译：提供了包括半导体衬底（1）和多个存储单元（19）的非易失性半导体存储器（30）和用于制造这种存储器的方法。每个存储单元（19）包括电荷捕获元件（5），栅极堆叠（20），氮化物间隔物（10）和电绝缘元件（21）。电荷捕获元件（5）设置在半导体衬底（1）上并且包括夹在底部氧化物层（2）和顶部氧化物层（4）之间的氮化物层（3），电荷俘获元件（5））具有彼此相对的两个侧壁（24）。栅极堆叠（20）布置在电荷捕获元件（5）的顶部上，栅极堆叠具有彼此相对的两个侧壁（25）。电绝缘元件（21）设置在电荷捕获元件（5）的相对侧壁（24）处并覆盖电荷捕获元件（5）的侧壁（24）。氮化物间隔物（10）覆盖电绝缘元件（21）并且布置在栅极堆叠（20）的相对侧壁（25）上以及电绝缘元件（21）上。

6. 发明申请

US20050003613A1 Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate 失效
标题翻译：一种制造具有电荷捕获存储单元和半导体衬底的半导体存储器的方法
公开(公告)号：US20050003613A1
公开(公告)日：2005-01-06
申请号：US10856414
申请日：2004-05-27
申请人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
发明人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
IPC分类号： H01L21/8246 , H01L27/115 , G11C17/00
CPC分类号： H01L27/11568 , H01L27/115
摘要： Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.
摘要翻译：导电材料被引入到字线（2）之间的间隙中，并且使用掩模（6）部分地移除，使得导电材料的残留部分（7）在每种情况下都填满相关间隙的一部分并产生与源/漏区（15）的电接触。对于导电材料的另外部分，可以形成用于制造工艺的对准标记。

7. 发明授权

US07145807B2 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US07145807B2
公开(公告)日：2006-12-05
申请号：US11072694
申请日：2005-03-04
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。

8. 发明申请

US20060223267A1 Method of production of charge-trapping memory devices 审中-公开
标题翻译：电荷俘获存储器件的生产方法
公开(公告)号：US20060223267A1
公开(公告)日：2006-10-05
申请号：US11095925
申请日：2005-03-31
申请人： Stefan Machill , Christoph Ludwig , Jan-Malte Schley , Gunther Wein , Jens-Uwe Sachse , Mathias Krause , Mark Isler , Joachim Deppe
发明人： Stefan Machill , Christoph Ludwig , Jan-Malte Schley , Gunther Wein , Jens-Uwe Sachse , Mathias Krause , Mark Isler , Joachim Deppe
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/40117
摘要： The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.
摘要翻译：主衬底表面的字线堆叠和中间区域的表面被氧氮化物衬垫覆盖。形成BPSG的侧壁间隔物，或者沉积另外的氮化物衬垫，并形成氧化物的间隔物。这些间隔物用于寻址电路的外围区域以注入掺杂的源极/漏极区域。氧氮化物降低了氮化物和半导体材料之间的应力，并且防止电荷载流子从氮化物的存储层渗透到衬里中。

9. 发明授权

US07411837B2 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US07411837B2
公开(公告)日：2008-08-12
申请号：US11600425
申请日：2006-11-16
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。

10. 发明申请

US20050195650A1 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US20050195650A1
公开(公告)日：2005-09-08
申请号：US11072694
申请日：2005-03-04
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region (2) that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域（2），其中信息被存储为有效参数的差异。

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