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1. 发明申请

US20050275059A1 Isolation trench arrangement 审中-公开
标题翻译：隔离槽排列
公开(公告)号：US20050275059A1
公开(公告)日：2005-12-15
申请号：US11145509
申请日：2005-06-03
申请人： Ricardo Mikalo , Christoph Ludwig , Pascal Deconinck , Jan-Malte Schley , Mark Isler , Jens-Uwe Sachse
发明人： Ricardo Mikalo , Christoph Ludwig , Pascal Deconinck , Jan-Malte Schley , Mark Isler , Jens-Uwe Sachse
IPC分类号： H01L21/74 , H01L21/76 , H01L21/763 , H01L29/00
CPC分类号： H01L21/763 , H01L21/743
摘要： Isolation trench arrangement, which isolates adjacent semiconductor structures (1), (2), an isolation trench (3) being formed in such a way that it penetrates from a substrate surface into the substrate volume (0) and has at least one insulating substance (20) and at least one conductive substance (21), and the conductive substance (21) is electrically conductively connected to the substrate (0) via an electrically conductive connection (22).
摘要翻译：隔离沟槽布置，其隔离相邻的半导体结构（1），（2），隔离沟槽（3），其形成为使得其从衬底表面穿透到衬底体积（0）中并且具有至少一个绝缘物质（20）和至少一个导电物质（21），并且所述导电物质（21）经由导电连接（22）导电地连接到所述基板（0）。

2. 发明申请

US20070086241A1 Evaluation circuit and evaluation method for the assessment of memory cell states 失效
标题翻译：用于评估存储单元状态的评估电路和评估方法
公开(公告)号：US20070086241A1
公开(公告)日：2007-04-19
申请号：US11543306
申请日：2006-10-04
申请人： Thomas Kern , Thomas Mikolajick , Jan-Malte Schley
发明人： Thomas Kern , Thomas Mikolajick , Jan-Malte Schley
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C11/5671 , G11C16/0475 , G11C27/005
摘要： An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.
摘要翻译：电子电路装置包括设置用于存储至少两个模拟电量的存储单元。第一评估电路耦合到存储单元并且被设置成使得其评估至少两个模拟电量并提供第一评估结果。第二评估电路耦合到存储单元并且被设置成使得其以预定阈值评估至少两个模拟电量中的至少一个并提供第二评估结果。

3. 发明申请

US20070086240A1 Measuring circuit and reading method for memory cells 失效
标题翻译：记忆单元的测量电路和读取方法
公开(公告)号：US20070086240A1
公开(公告)日：2007-04-19
申请号：US11542755
申请日：2006-10-04
申请人： Thomas Kern , Thomas Mikolajick , Jan-Malte Schley
发明人： Thomas Kern , Thomas Mikolajick , Jan-Malte Schley
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0475
摘要： An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.
摘要翻译：电子电路装置包括至少一个可存储至少两个电量的存储元件。开关单元电连接到存储元件并且具有至少一个第一电路路径和第二电路路径。存储单元具有第一部分存储单元和第二部分存储单元。每个部分存储单元设置用于存储至少一个电量。开关单元被设置成使得其可以顺序地将沿着第一电路路径的至少两个电量中的第一个顺序地传递到第一部分存储单元，并且沿着第二电路顺序地通过至少两个电量中的第二个到第二部分存储单元的电路路径。

4. 发明申请

US20070058443A1 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US20070058443A1
公开(公告)日：2007-03-15
申请号：US11600425
申请日：2006-11-16
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。

5. 发明授权

US07144776B1 Charge-trapping memory device 失效
标题翻译：电荷俘获存储器件
公开(公告)号：US07144776B1
公开(公告)日：2006-12-05
申请号：US11141254
申请日：2005-05-31
申请人： Ricardo Pablo Mikalo , Erwin Schroer , Günther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Andreas Kleint
发明人： Ricardo Pablo Mikalo , Erwin Schroer , Günther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Andreas Kleint
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.
摘要翻译：氧化区域布置在半导体材料的衬底和氮化物衬垫之间，其覆盖存储单元阵列的字线堆叠和衬底的中间区域，并且被提供以将氮化物衬垫与衬底和存储器层序列分离的电介质材料，用于电荷捕获。氮化物衬垫在形成用于外围区域的侧壁间隔物中用作蚀刻停止层，以产生寻址电路的晶体管的源极/漏极结。

6. 发明申请

US20060223267A1 Method of production of charge-trapping memory devices 审中-公开
标题翻译：电荷俘获存储器件的生产方法
公开(公告)号：US20060223267A1
公开(公告)日：2006-10-05
申请号：US11095925
申请日：2005-03-31
申请人： Stefan Machill , Christoph Ludwig , Jan-Malte Schley , Gunther Wein , Jens-Uwe Sachse , Mathias Krause , Mark Isler , Joachim Deppe
发明人： Stefan Machill , Christoph Ludwig , Jan-Malte Schley , Gunther Wein , Jens-Uwe Sachse , Mathias Krause , Mark Isler , Joachim Deppe
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/40117
摘要： The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.
摘要翻译：主衬底表面的字线堆叠和中间区域的表面被氧氮化物衬垫覆盖。形成BPSG的侧壁间隔物，或者沉积另外的氮化物衬垫，并形成氧化物的间隔物。这些间隔物用于寻址电路的外围区域以注入掺杂的源极/漏极区域。氧氮化物降低了氮化物和半导体材料之间的应力，并且防止电荷载流子从氮化物的存储层渗透到衬里中。

7. 发明授权

US07411837B2 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US07411837B2
公开(公告)日：2008-08-12
申请号：US11600425
申请日：2006-11-16
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。

8. 发明申请

US20060267078A1 CHARGE-TRAPPING MEMORY DEVICE 失效
标题翻译：充电跟踪存储器件
公开(公告)号：US20060267078A1
公开(公告)日：2006-11-30
申请号：US11141254
申请日：2005-05-31
申请人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
发明人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.
摘要翻译：氧化区域布置在半导体材料的衬底和氮化物衬垫之间，其覆盖存储单元阵列的字线堆叠和衬底的中间区域，并且被提供以将氮化物衬垫与衬底和存储器层序列分离的电介质材料，用于电荷捕获。氮化物衬垫在形成用于外围区域的侧壁间隔物中用作蚀刻停止层，以产生寻址电路的晶体管的源极/漏极结。

9. 发明申请

US20050195650A1 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US20050195650A1
公开(公告)日：2005-09-08
申请号：US11072694
申请日：2005-03-04
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region (2) that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域（2），其中信息被存储为有效参数的差异。

10. 发明授权

US07646647B2 Measuring circuit and reading method for memory cells 失效
标题翻译：记忆单元的测量电路和读取方法
公开(公告)号：US07646647B2
公开(公告)日：2010-01-12
申请号：US11542755
申请日：2006-10-04
申请人： Thomas Kern , Thomas Mikolajick , Jan-Malte Schley
发明人： Thomas Kern , Thomas Mikolajick , Jan-Malte Schley
IPC分类号： G11C11/03
CPC分类号： G11C16/26 , G11C16/0475
摘要： An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial storage unit and a second partial storage unit. Each partial storage unit is set up for storing at least one electrical quantity. The switching unit is set up in such a way that it can sequentially pass a first one of the at least two electrical quantities along the first circuit path to the first partial storage unit and a second one of the at least two electrical quantities along the second circuit path to the second partial storage unit.
摘要翻译：电子电路装置包括至少一个可存储至少两个电量的存储元件。开关单元电连接到存储元件并且具有至少一个第一电路路径和第二电路路径。存储单元具有第一部分存储单元和第二部分存储单元。每个部分存储单元设置用于存储至少一个电量。开关单元被设置成使得其可以顺序地将沿着第一电路路径的至少两个电量中的第一个顺序地传递到第一部分存储单元，并且沿着第二电路顺序地通过至少两个电量中的第二个到第二部分存储单元的电路路径。

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