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1. 发明申请

US20090034216A1 LOW PROFILE DIMM BOARD 有权
标题翻译：低配置DIMM板
公开(公告)号：US20090034216A1
公开(公告)日：2009-02-05
申请号：US11831377
申请日：2007-07-31
申请人： Christian Petersen , Robert J. Blakely , Ray Woodward
发明人： Christian Petersen , Robert J. Blakely , Ray Woodward
IPC分类号： H05K7/00
CPC分类号： H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A primary memory board is disclosed. The primary memory board comprises a printed circuit board (PCB) having a front side and a back side, a plurality of DIMM surface mount connectors, and at least one component. The plurality of DIMM surface mount connectors are mounted on the front side of the PCB. The at least one component is mounted on the back side of the PCB and is positioned opposite the location of at least one of the plurality of DIMM surface mount connectors mounted on the front side of the PCB.
摘要翻译：公开了一种主存储器板。主存储器板包括具有前侧和后侧的印刷电路板（PCB），多个DIMM表面安装连接器和至少一个部件。多个DIMM表面贴装连接器安装在PCB的正面。至少一个组件安装在PCB的背面，并且与安装在PCB正面上的多个DIMM表面安装连接器中的至少一个的位置相对。

2. 发明授权

US07793043B2 Buffered memory architecture 有权
标题翻译：缓冲内存架构
公开(公告)号：US07793043B2
公开(公告)日：2010-09-07
申请号：US11509449
申请日：2006-08-24
申请人： Robert J. Blakely , Ray Woodward , Christian Petersen
发明人： Robert J. Blakely , Ray Woodward , Christian Petersen
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G11C5/02
摘要： A memory architecture includes at least one unbuffered dual inline memory module (DIMM). At least one advanced memory buffer (AMB) provides an interface between the at least one DIMM and a host memory controller.
摘要翻译：存储器架构包括至少一个无缓冲双列直插式存储器模块（DIMM）。至少一个高级内存缓冲区（AMB）提供至少一个DIMM和主机内存控制器之间的接口。

3. 发明授权

US07692930B2 Low profile DIMM board 有权
标题翻译：薄型DIMM板
公开(公告)号：US07692930B2
公开(公告)日：2010-04-06
申请号：US11831377
申请日：2007-07-31
申请人： Christian Petersen , Robert J. Blakely , Ray Woodward
发明人： Christian Petersen , Robert J. Blakely , Ray Woodward
IPC分类号： H05K1/18
CPC分类号： H05K1/181 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A primary memory board is disclosed. The primary memory board comprises a printed circuit board (PCB) having a front side and a back side, a plurality of DIMM surface mount connectors, and at least one component. The plurality of DIMM surface mount connectors are mounted on the front side of the PCB. The at least one component is mounted on the back side of the PCB and is positioned opposite the location of at least one of the plurality of DIMM surface mount connectors mounted on the front side of the PCB.
摘要翻译：公开了一种主存储器板。主存储器板包括具有前侧和后侧的印刷电路板（PCB），多个DIMM表面安装连接器和至少一个部件。多个DIMM表面贴装连接器安装在PCB的正面。至少一个组件安装在PCB的背面，并且与安装在PCB正面上的多个DIMM表面安装连接器中的至少一个的位置相对。

4. 发明申请

US20080052462A1 Buffered memory architecture 有权
标题翻译：缓冲内存架构
公开(公告)号：US20080052462A1
公开(公告)日：2008-02-28
申请号：US11509449
申请日：2006-08-24
申请人： Robert J. Blakely , Ray Woodward , Christian Petersen
发明人： Robert J. Blakely , Ray Woodward , Christian Petersen
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G11C5/02
摘要： A memory architecture includes at least one unbuffered dual inline memory module (DIMM). At least one advanced memory buffer (AMB) provides an interface between the at least one DIMM and a host memory controller.
摘要翻译：存储器架构包括至少一个无缓冲双列直插式存储器模块（DIMM）。至少一个高级内存缓冲区（AMB）提供至少一个DIMM和主机内存控制器之间的接口。

5. 发明授权

US06381663B1 Mechanism for implementing bus locking with a mixed architecture 失效
标题翻译：用混合架构实现总线锁定的机制
公开(公告)号：US06381663B1
公开(公告)日：2002-04-30
申请号：US09277718
申请日：1999-03-26
申请人： John A. Morrison , Robert J. Blakely , Eric M. Rentschler , John R. Feehrer
发明人： John A. Morrison , Robert J. Blakely , Eric M. Rentschler , John R. Feehrer
IPC分类号： G06F1300
CPC分类号： G06F13/1673 , G06F13/4059
摘要： An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.
摘要翻译：一种在具有混合架构的计算机系统中允许总线锁定的装置和方法。混合架构包括耦合到处理器的第一总线，其可以使用总线锁定或高速缓存行锁定来运行应用。该设备将第一总线与不支持总线锁定的第二总线接口。该装置在呈现锁定事务时有效地在第二总线上实现总线锁定。

6. 发明授权

US07844841B2 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US07844841B2
公开(公告)日：2010-11-30
申请号：US11742440
申请日：2007-04-30
申请人： Robert J. Blakely , Samuel M. Babb , Bradley D. Winick , Robert B. Smith
发明人： Robert J. Blakely , Samuel M. Babb , Bradley D. Winick , Robert B. Smith
IPC分类号： G06F1/00 , H01F19/00 , H02J1/00 , H02M7/00
CPC分类号： G06F1/26 , H02J2001/008 , Y10T307/50
摘要： An electronic device is disclosed herein. An embodiment of the electronic device comprises an electronic component, wherein the electronic component is operated by a DC voltage. The electronic component comprises an AC to DC converter that converts an AC voltage to the DC voltage, wherein the RMS value of the AC voltage is greater than the DC voltage. The electronic device further comprises a power supply comprising an input and an output. The input is connectable to a line voltage and the output is connected to the AC to DC converter of electronic component. The AC voltage is output by the output of the power supply.
摘要翻译：本文公开了一种电子设备。电子设备的实施例包括电子部件，其中电子部件由DC电压操作。电子部件包括将AC电压转换为DC电压的AC-DC转换器，其中AC电压的RMS值大于DC电压。该电子设备还包括一个包括输入和输出的电源。输入可连接到线路电压，输出端连接到电子元件的交直流转换器。交流电压由电源输出输出。

7. 发明授权

US06470408B1 Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors 失效
标题翻译：通过APIC总线将中断传送到IA-32处理器的装置和方法
公开(公告)号：US06470408B1
公开(公告)日：2002-10-22
申请号：US09292131
申请日：1999-04-14
申请人： John A. Morrison , Robert J. Blakely , Leo J. Embry , Michael S. Allison
发明人： John A. Morrison , Robert J. Blakely , Leo J. Embry , Michael S. Allison
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An apparatus and a method are provided to distribute interrupts from a system bus to Intel® Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.
摘要翻译：提供了一种装置和方法来将中断从系统总线分配到Intel（R）Architecture（IA）-32应用处理器。该装置包括将处理器总线耦合到系统总线的桥。此外，桥接器通过APIC总线耦合到高级可编程中断控制器（APIC）。桥接器监视系统总线进行中断，并将所选中断事务转换为APIC消息。然后桥接器将APIC消息发送到APIC总线。每个应用处理器也耦合到许多APIC总线之一。作为中断事务的目标的应用处理器接收APIC消息并执行中断处理程序。该装置和方法还包括中断事务缓冲和限制。

8. 发明申请

US20080270808A1 Electronic Device 有权
标题翻译：电子设备
公开(公告)号：US20080270808A1
公开(公告)日：2008-10-30
申请号：US11742440
申请日：2007-04-30
申请人： Robert J. Blakely , Samuel M. Babb , Bradley D. Winick , Robert B. Smith
发明人： Robert J. Blakely , Samuel M. Babb , Bradley D. Winick , Robert B. Smith
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , H02J2001/008 , Y10T307/50
摘要： An electronic device is disclosed herein. An embodiment of the electronic device comprises an electronic component, wherein the electronic component is operated by a DC voltage. The electronic component comprises an AC to DC converter that converts an AC voltage to the DC voltage, wherein the RMS value of the AC voltage is greater than the DC voltage. The electronic device further comprises a power supply comprising an input and an output. The input is connectable to a line voltage and the output is connected to the AC to DC converter of electronic component. The AC voltage is output by the output of the power supply.
摘要翻译：本文公开了一种电子设备。电子设备的实施例包括电子部件，其中电子部件由DC电压操作。电子部件包括将AC电压转换为DC电压的AC-DC转换器，其中AC电压的RMS值大于DC电压。电子设备还包括电源，其包括输入和输出。输入可连接到线路电压，输出端连接到电子元件的交直流转换器。交流电压由电源输出输出。

9. 发明授权

US06618266B2 Method for high-density, low-via-count, decoupling capacitor placement 失效
公开(公告)号：US06618266B2
公开(公告)日：2003-09-09
申请号：US09800282
申请日：2001-03-06
申请人： Robert J. Blakely , John S. Atkinson
发明人： Robert J. Blakely , John S. Atkinson
IPC分类号： H05K118
CPC分类号： H05K1/113 , H05K1/0231 , H05K1/115 , H05K2201/09381 , H05K2201/0979 , H05K2201/10522 , H05K2201/10545 , H05K2201/10636 , Y02P70/611
摘要： A capacitor mounting method and resulting printed circuit board that increases the mounting density of both vias and decoupling capacitors is presented. Vias are shared between capacitors mounted on the top and bottom of the printed circuit board. This arrangement allows increased decoupling capacitor density and avoids the current doubling problem when shared vias are connected with capacitors installed on the same side of the board.

10. 发明授权

US07721133B2 Systems and methods of synchronizing reference frequencies 有权
标题翻译：同步参考频率的系统和方法
公开(公告)号：US07721133B2
公开(公告)日：2010-05-18
申请号：US11412384
申请日：2006-04-27
申请人： Robert J Brooks , Robert J. Blakely , Karl J. Bois
发明人： Robert J Brooks , Robert J. Blakely , Karl J. Bois
IPC分类号： G06F1/12 , H03L7/00
CPC分类号： G06F1/10 , G06F1/12 , G06F11/1604
摘要： System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.
摘要翻译：公开了同步参考频率的系统和方法。在示例性实现中，方法可以包括为多个操作组件中的每一个提供单独的参考频率。该方法还可以包括以模块化的容错电路拓扑将彼此分开的参考频率相互连接。该方法还可以包括使单独的参考频率同步，使得每个操作分量以相同的频率工作。

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