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1. 发明授权

US08400853B2 Semiconductor chip and method of repair design of the same 有权
标题翻译：半导体芯片和维修方法的设计一样
公开(公告)号：US08400853B2
公开(公告)日：2013-03-19
申请号：US12778120
申请日：2010-05-12
申请人： Chizu Matsumoto , Kaname Yamasaki , Michinobu Nakao , Yoshikazu Saitou
发明人： Chizu Matsumoto , Kaname Yamasaki , Michinobu Nakao , Yoshikazu Saitou
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
摘要翻译：提供了一种修复电路，实现混合多种修复方法的组修复和用于制作商品边缘的修复设计方法。在安装多个RAM的芯片中，提供了考虑到芯片产量和面积增加的权衡以及安装修复电路的修复电路和修复设计方法。修复电路分别实现了可以选择修复电路的存在的混合多种修复方法的组修复，以及在修复电路是否在芯片中的RAMS时分别从I / O，列和行修复中的一种或多种修复方法安装。修复电路通过将安装修复电路的RAM分类为多个RAM组来对每个RAM组进行修复。此外，提供了使晶片中获得的多个芯片的数量的修复方法和RAM分组方法的估计方法。

2. 发明申请

US20100290299A1 SEMICONDUCTOR CHIP AND METHOD OF REPAIR DESIGN OF THE SAME 有权
标题翻译：半导体芯片及其修复方法
公开(公告)号：US20100290299A1
公开(公告)日：2010-11-18
申请号：US12778120
申请日：2010-05-12
申请人： Chizu MATSUMOTO , Kaname Yamasaki , Michinobu Nakao , Yoshikazu Saitou
发明人： Chizu MATSUMOTO , Kaname Yamasaki , Michinobu Nakao , Yoshikazu Saitou
IPC分类号： G11C29/00 , G11C29/12 , G06F17/50
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
摘要翻译：提供了实现“混合多重修复方法的组修复”的维修电路和用于制造商品边缘的修理设计方法。在安装多个RAM的芯片中，提供了考虑到芯片产量和面积增加的权衡以及安装修复电路的修复电路和修复设计方法。分别在芯片上的RAMS上实现“可以选择修复电路的存在的”混合多重修复方法的组修复“以及I / O，列和行修复中的一种或多种修复方法的修复电路电路安装。修复电路通过将安装修复电路的RAM分类为多个RAM组来对每个RAM组进行修复。此外，提供了使晶片中获得的多个芯片的数量的修复方法和RAM分组方法的估计方法。

3. 发明授权

US06756814B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US06756814B2
公开(公告)日：2004-06-29
申请号：US10345242
申请日：2003-01-16
申请人： Yoshikazu Saitou , Kenichi Osada
发明人： Yoshikazu Saitou , Kenichi Osada
IPC分类号： H03K19175
CPC分类号： H03K19/0016
摘要： The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.
摘要翻译：本发明旨在简化用于在抑制亚阈值电流的同时固定逻辑门的输出逻辑的电路。逻辑电路具有能够根据输入控制信号中断到逻辑门的电源的n沟道型第一晶体管，以及能够将逻辑门的输出节点固定为高电平的p沟道型第二晶体管与第一晶体管的电源中断操作互锁，并且将第一晶体管的阈值设置为高于作为逻辑门的组件的晶体管的阈值。用于中断对逻辑门的电源的装置由第一晶体管实现，并且通过第二晶体管实现将逻辑门的输出节点固定为高电平的装置，从而简化用于固定逻辑门的输出逻辑的电路同时抑制亚阈值电流。

4. 发明申请

US20090245004A1 SEMICONDUCTOR DEVICE INCLUDING MULTI-CHIP 失效
标题翻译：包括多芯片的半导体器件
公开(公告)号：US20090245004A1
公开(公告)日：2009-10-01
申请号：US12482579
申请日：2009-06-11
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译：为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

5. 发明授权

US06928512B2 Semiconductor device with non-volatile memory and random access memory 有权
标题翻译：具有非易失性存储器和随机存取存储器的半导体器件
公开(公告)号：US06928512B2
公开(公告)日：2005-08-09
申请号：US10163364
申请日：2002-06-06
申请人： Kazushige Ayukawa , Seiji Miura , Tetsuya Iwamura , Kouichi Hoshi , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Tetsuya Iwamura , Kouichi Hoshi , Yoshikazu Saitou
IPC分类号： G11C11/41 , G06F12/00 , G06F12/06 , G11C5/00 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/408
CPC分类号： G11C11/4087 , G11C11/005 , G11C11/406 , G11C2207/2245 , H01L25/0652 , H01L25/0655 , H01L2224/06135 , H01L2224/06156 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49175 , H01L2924/13091 , H01L2924/15311 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.
摘要翻译：非易失性存储器，SRAM，DRAM和控制电路被模块化成单个封装。控制电路将地址分配给SRAM，并将DRAM的地址分配给SRAM，并将需要长时间保持的数据保存在SRAM中。 DRAM的两个芯片映射到相同的地址空间并交替刷新。多个芯片被布置为使得它们相互层压，并且它们通过BGA或芯片间接合来布线。

6. 发明申请

US20120262992A1 SEMICONDUCTOR DEVICE INCLUDING MULTI-CHIP 失效
标题翻译：包括多芯片的半导体器件
公开(公告)号：US20120262992A1
公开(公告)日：2012-10-18
申请号：US13533003
申请日：2012-06-26
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C16/04
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译：为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

7. 发明授权

US08223578B2 Semiconductor device including multi-chip 失效
标题翻译：半导体器件包括多芯片
公开(公告)号：US08223578B2
公开(公告)日：2012-07-17
申请号：US12482579
申请日：2009-06-11
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C5/06
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译：为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

8. 发明申请

US20050128853A1 Semiconductor device including multi-chip 有权
公开(公告)号：US20050128853A1
公开(公告)日：2005-06-16
申请号：US11037088
申请日：2005-01-19
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C11/41 , G11C5/00 , G11C8/12 , G11C11/00 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C16/04 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18 , G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

9. 发明授权

US06587393B2 Semiconductor device including multi-chip 有权
公开(公告)号：US06587393B2
公开(公告)日：2003-07-01
申请号：US10140945
申请日：2002-05-09
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C800
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

10. 发明授权

US08711650B2 Semiconductor device including multi-chip 失效
标题翻译：半导体器件包括多芯片
公开(公告)号：US08711650B2
公开(公告)日：2014-04-29
申请号：US13533003
申请日：2012-06-26
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译：为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

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