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1. 发明授权

US5958508A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5958508A
公开(公告)日：1999-09-28
申请号：US828635
申请日：1997-03-31
申请人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
发明人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
IPC分类号： H01L29/43 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/205 , H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , C23C16/00 , H01L21/285
CPC分类号： C23C16/45523 , H01L21/76895 , H01L28/60
摘要： A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.
摘要翻译：金属半导体层（26）形成在绝缘层（20）上，使得金属半导体层（26）被分级以在整个层中具有不同量的半导体和金属。在一个实施例中，金属半导体层（26）在层的下表面和上表面附近具有相对较高的硅含量。在中点处，该层接近化学计量的硅化钨。在另一个实施方案中，形成具有更靠近下表面的氮并且在上表面附近基本上不含氮的金属 - 半导体 - 氮层。层（26）可以使用化学气相沉积或溅射形成。

2. 发明授权

US5824579A Method of forming shared contact structure 失效
标题翻译：形成共同接触结构的方法
公开(公告)号：US5824579A
公开(公告)日：1998-10-20
申请号：US632207
申请日：1996-04-15
申请人： Chitra K. Subramanian , James D. Hayden
发明人： Chitra K. Subramanian , James D. Hayden
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , Y10S148/02
摘要： A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such that they are physically isolated from each other. The second coupling layer (60) is formed such that it is in physical contact with the active region (33). A contact opening (45) is formed, which exposes a portion of coupling layers (59, 60). The third coupling layer (46) is then formed so that it is in electrical contact with the second coupling layer (60) and the first coupling layer (59).
摘要翻译：形成共享接触结构（30）以将三个耦合层（59,60,46）彼此电连接到半导体衬底（31）中的有源区（33）。形成第一耦合层（59）和第二耦合层（60），使得它们彼此物理隔离。第二耦合层（60）形成为与活性区域（33）物理接触。形成接触开口（45），其露出一部分耦合层（59,60）。然后形成第三耦合层（46），使得其与第二耦合层（60）和第一耦合层（59）电接触。

3. 发明授权

US5668021A Process for fabricating a semiconductor device having a segmented channel region 失效
标题翻译：具有分段通道区域的半导体器件的制造方法
公开(公告)号：US5668021A
公开(公告)日：1997-09-16
申请号：US658972
申请日：1996-06-04
申请人： Chitra K. Subramanian , James D. Hayden
发明人： Chitra K. Subramanian , James D. Hayden
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/42376 , H01L29/66553 , H01L29/66537 , H01L29/7833
摘要： A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).
摘要翻译：制造具有分段沟道区（48）的MOS器件（44）的工艺包括制造复合MOS栅电极（46）。通过在第一多晶硅层（14）上形成开口（18）和绝缘层（16）来形成分段通道区域（48）和MOS栅电极（46）。形成在半导体衬底（10）中的MOS栅电极（46）和掩埋结区（24）的横向范围由第一侧壁间隔件（22）和与第一侧壁间隔件（32）相邻形成的第二侧壁间隔件侧壁间隔件（22）。

4. 发明授权

US5665202A Multi-step planarization process using polishing at two different pad pressures 失效
标题翻译：使用两种不同压力下的抛光进行多步平面化处理
公开(公告)号：US5665202A
公开(公告)日：1997-09-09
申请号：US562440
申请日：1995-11-24
申请人： Chitra K. Subramanian , Asanga H. Perera , James D. Hayden , Subramoney V. Iyer
发明人： Chitra K. Subramanian , Asanga H. Perera , James D. Hayden , Subramoney V. Iyer
IPC分类号： H01L21/3105 , H01L21/306
CPC分类号： H01L21/31053
摘要： A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill material (40) is removed leaving a remaining portion (44). The pad pressure of a CMP apparatus (20) is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion (44) is removed, while operating the CMP apparatus (20) at a second pad pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion (44) is removed by an etching process using a portion (46) of second planarization layer (42).
摘要翻译：抛光平面化覆盖半导体衬底（30）的填充材料（40）的工艺包括多步抛光工艺。在一个实施例中，第二平坦化层（42）沉积在填充材料（40）上，并且去除填充材料（40）的一部分，留下剩余部分（44）。调整CMP装置（20）的衬垫压力，使得在抛光过程中产生第一压力。然后，在第二焊盘压力下操作CMP装置（20）的同时去除剩余部分（44）。通过在第二抛光步骤期间减小垫压力来维持抛光工艺的选择性。在第二实施例中，在执行第一抛光步骤之后，通过使用第二平坦化层（42）的部分（46）的蚀刻工艺去除剩余部分（44）。

5. 发明授权

US5413948A Method for forming a dual transistor structure 失效
标题翻译：形成双晶体管结构的方法
公开(公告)号：US5413948A
公开(公告)日：1995-05-09
申请号：US209763
申请日：1994-03-14
申请人： James R. Pfiester , James D. Hayden
发明人： James R. Pfiester , James D. Hayden
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/786 , H01L21/336
CPC分类号： H01L29/78696 , H01L27/11 , H01L27/1108 , H01L29/42376 , H01L29/78642 , Y10S257/903
摘要： A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.
摘要翻译：晶体管结构（10）具有基板（12）。第一晶体管形成在具有源极区（38），漏极区（30）和由第一间隔物（26a）形成的栅电极的衬底（12）内。第二晶体管由源极区（38），漏极区（28）和由第二间隔物（26a）形成的栅极形成在衬底（12）内。第三晶体管形成在第一晶体管的上方。第三晶体管具有源极区（34a），漏极区（34c），沟道区（34b）和由第一间隔物（26a）形成的栅电极。第四晶体管形成在第二晶体管的上方。第四晶体管具有源极区（34a），漏极区（34c），沟道区（34b）和由第二间隔物（26a）形成的栅电极。第一，第二，第三和第四晶体管可以互连以形成小型静态随机存取存储器（SRAM）单元的一部分。

6. 发明授权

US5398200A Vertically formed semiconductor random access memory device 失效
标题翻译：垂直形成的半导体随机存取存储器件
公开(公告)号：US5398200A
公开(公告)日：1995-03-14
申请号：US183086
申请日：1994-01-18
申请人： Carlos A. Mazure , Jon T. Fitch , James D. Hayden , Keith E. Witek
发明人： Carlos A. Mazure , Jon T. Fitch , James D. Hayden , Keith E. Witek
IPC分类号： H01L21/768 , H01L29/78 , H01L27/01
CPC分类号： H01L21/76897 , H01L27/1108 , H01L27/1112 , H01L29/66666 , H01L29/7827 , H01L27/0688 , Y10S257/904
摘要： A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.
摘要翻译：形成具有基板（12）的半导体存储器件。在衬底（12）内形成扩散（14）。形成第一垂直晶体管堆叠（122）。形成第二垂直晶体管堆叠（124）。第一垂直晶体管堆叠（122）具有位于晶体管（104）下面的晶体管（100）。第二垂直晶体管堆叠（124）具有位于晶体管（106）下方的晶体管（102）。晶体管（100和104）串联连接，晶体管（102和106）串联连接。在优选形式中，晶体管（100和102）电连接作为用于半导体存储器件的锁存晶体管，并且晶体管（106和104）作为传输晶体管连接。两个垂直堆叠（126和128）形成用于半导体存储器件的电互连（118和120）和电阻器件（134和138）。

7. 发明授权

US5393689A Process for forming a static-random-access memory cell 失效
标题翻译：形成静态随机存取存储单元的过程
公开(公告)号：US5393689A
公开(公告)日：1995-02-28
申请号：US209170
申请日：1994-02-28
申请人： James R. Pfiester , James D. Hayden
发明人： James R. Pfiester , James D. Hayden
IPC分类号： H01L27/11 , H01L21/8244 , H01L21/70
CPC分类号： H01L27/11 , Y10S257/903
摘要： An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.
摘要翻译：形成SRAM单元，使得与与锁存晶体管相邻的锁存通道停止区域相比，与通过晶体管相邻的通过通道停止区域具有较高的掺杂浓度。在一个实施例中，通道通道停止区域是使用两个通道停止掺杂步骤形成的，而锁存通道停止区域仅在一个通道停止掺杂步骤期间形成。掺杂步骤可以在形成场隔离之前或之后进行。与锁存通道停止区域相比，较高的掺杂浓度使来自通道 - 停止区域的掺杂剂从场隔离的边缘横向延伸。该过程可以适用于几乎任何类型的现场隔离过程。

8. 发明授权

US5330929A Method of making a six transistor static random access memory cell 失效
标题翻译：制造六晶体管静态随机存取存储单元的方法
公开(公告)号：US5330929A
公开(公告)日：1994-07-19
申请号：US955785
申请日：1992-10-05
申请人： James R. Pfiester , James D. Hayden
发明人： James R. Pfiester , James D. Hayden
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L27/1108 , Y10S148/059
摘要： The present invention includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise an active region and a first layer. The active region including a first segment, a second segment, and a third segment, wherein 1) the first segment has an adjacent end and a distal end; 2) the second segment is generally parallel to the first segment, and has an adjacent end and a distal end; and 3) the third segment is generally perpendicular to the first direction, wherein the adjacent end of the first segment lies near one end of the third segment, wherein the adjacent end of the second segment lies near the other end of the third segment. The first layer has the a shape similar to the active region except that the first layer does not lie over the first and second segments near the distal ends. The present invention also includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise shared gate electrodes that overlap one another without electrically contacting each other.
摘要翻译：本发明包括静态随机存取存储器单元和形成存储单元的方法，其中存储单元可以包括有源区和第一层。所述活动区域包括第一段，第二段和第三段，其中1）所述第一段具有相邻端和远端; 2）第二段通常平行于第一段，并具有相邻端和远端; 以及3）所述第三段通常垂直于所述第一方向，其中所述第一段的相邻端靠近所述第三段的一端，其中所述第二段的相邻端靠近所述第三段的另一端。第一层具有类似于活性区域的形状，除了第一层不位于远端附近的第一和第二区段之外。本发明还包括静态随机存取存储器单元和形成存储单元的方法，其中存储单元可以包括彼此重叠而不彼此电接触的共享栅电极。

9. 发明授权

US5252849A Transistor useful for further vertical integration and method of formation 失效
标题翻译：晶体管有助于进一步垂直整合和形成方法
公开(公告)号：US5252849A
公开(公告)日：1993-10-12
申请号：US844037
申请日：1992-03-02
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek , James D. Hayden
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek , James D. Hayden
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/336 , H01L21/822 , H01L27/06 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/10 , H01L29/72
CPC分类号： H01L29/66287 , H01L21/8221 , H01L27/0688 , H01L29/66666 , H01L29/6675 , H01L29/732 , H01L29/7827
摘要： A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).
摘要翻译：晶体管形成为双极晶体管（10）或MOS晶体管（11）。每个晶体管（10或11）具有衬底（12）。双极晶体管（10）具有位于控制电极（28）下方的第一电流电极（26）和覆盖控制电极（28）的第二电流电极（32）。 MOS晶体管（11）具有位于沟道区（56）下面的第一电流电极（54）和覆盖沟道区（56）的源极轻掺杂区（58）和源极重掺杂区（60）。控制电极导电层（40）横向邻近侧壁电介质层（48），侧壁电介质层（48）横向邻近沟道区域（56）。导电层（40）用作晶体管（11）的栅电极。每个晶体管（10和11）是垂直集成的，例如在垂直集成的BiMOS电路中。晶体管（10和11）可通过隔离电隔离（64和66）。

10. 发明授权

US5567958A High-performance thin-film transistor and SRAM memory cell 失效
标题翻译：高性能薄膜晶体管和SRAM存储单元
公开(公告)号：US5567958A
公开(公告)日：1996-10-22
申请号：US452944
申请日：1995-05-31
申请人： Marius Orlowski , James D. Hayden , Bich-Yen Nguyen
发明人： Marius Orlowski , James D. Hayden , Bich-Yen Nguyen
IPC分类号： H01L21/336 , H01L27/11 , H01L29/786 , H01L29/78
CPC分类号： H01L27/1108 , H01L29/66757 , H01L29/78696 , Y10S257/903
摘要： A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.
摘要翻译：薄膜晶体管和SRAM存储单元包括由开口（22）和上覆绝缘层（11）分开的薄膜源区和漏区（12,14）。薄膜通道层（16）覆盖薄膜源区和漏区（12,14），绝缘层（11）的一部分由开口（22）露出。薄膜栅电极（20）位于开口（22）中并且在薄膜通道层（16）中限定薄膜通道区（24）。薄膜栅电极（20）通过栅介质层（18）与薄膜沟道区（24）分离。薄膜通道区域（24）沿薄膜源极和漏极区域（12,14）的垂直壁表面（26,28）延伸，为薄膜晶体管提供延长的沟道长度。

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