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1. 发明授权

US5308782A Semiconductor memory device and method of formation 失效
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US5308782A
公开(公告)日：1994-05-03
申请号：US966643
申请日：1992-10-26
申请人： Carlos A. Mazure , Jon T. Fitch , James D. Hayden , Keith E. Witek
发明人： Carlos A. Mazure , Jon T. Fitch , James D. Hayden , Keith E. Witek
IPC分类号： H01L27/00 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/70
CPC分类号： H01L29/66666 , H01L21/8221 , H01L27/0688 , H01L27/088 , H01L29/6675 , H01L29/7827 , H01L29/7834
摘要： A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.
摘要翻译：形成具有基板（12）的半导体存储器件。在衬底（12）内形成扩散（14）。形成第一垂直晶体管堆叠（122）。形成第二垂直晶体管堆叠（124）。第一垂直晶体管堆叠（122）具有位于晶体管（104）下面的晶体管（100）。第二垂直晶体管堆叠（124）具有位于晶体管（106）下方的晶体管（102）。晶体管（100和104）串联连接，晶体管（102和106）串联连接。在优选形式中，晶体管（100和102）电连接作为用于半导体存储器件的锁存晶体管，并且晶体管（106和104）作为传输晶体管连接。两个垂直堆叠（126和128）形成用于半导体存储器件的电互连（118和120）和电阻器件（134和138）。

2. 发明授权

US5398200A Vertically formed semiconductor random access memory device 失效
标题翻译：垂直形成的半导体随机存取存储器件
公开(公告)号：US5398200A
公开(公告)日：1995-03-14
申请号：US183086
申请日：1994-01-18
申请人： Carlos A. Mazure , Jon T. Fitch , James D. Hayden , Keith E. Witek
发明人： Carlos A. Mazure , Jon T. Fitch , James D. Hayden , Keith E. Witek
IPC分类号： H01L21/768 , H01L29/78 , H01L27/01
CPC分类号： H01L21/76897 , H01L27/1108 , H01L27/1112 , H01L29/66666 , H01L29/7827 , H01L27/0688 , Y10S257/904
摘要： A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.
摘要翻译：形成具有基板（12）的半导体存储器件。在衬底（12）内形成扩散（14）。形成第一垂直晶体管堆叠（122）。形成第二垂直晶体管堆叠（124）。第一垂直晶体管堆叠（122）具有位于晶体管（104）下面的晶体管（100）。第二垂直晶体管堆叠（124）具有位于晶体管（106）下方的晶体管（102）。晶体管（100和104）串联连接，晶体管（102和106）串联连接。在优选形式中，晶体管（100和102）电连接作为用于半导体存储器件的锁存晶体管，并且晶体管（106和104）作为传输晶体管连接。两个垂直堆叠（126和128）形成用于半导体存储器件的电互连（118和120）和电阻器件（134和138）。

3. 发明授权

US5252849A Transistor useful for further vertical integration and method of formation 失效
标题翻译：晶体管有助于进一步垂直整合和形成方法
公开(公告)号：US5252849A
公开(公告)日：1993-10-12
申请号：US844037
申请日：1992-03-02
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek , James D. Hayden
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek , James D. Hayden
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/336 , H01L21/822 , H01L27/06 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/10 , H01L29/72
CPC分类号： H01L29/66287 , H01L21/8221 , H01L27/0688 , H01L29/66666 , H01L29/6675 , H01L29/732 , H01L29/7827
摘要： A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).
摘要翻译：晶体管形成为双极晶体管（10）或MOS晶体管（11）。每个晶体管（10或11）具有衬底（12）。双极晶体管（10）具有位于控制电极（28）下方的第一电流电极（26）和覆盖控制电极（28）的第二电流电极（32）。 MOS晶体管（11）具有位于沟道区（56）下面的第一电流电极（54）和覆盖沟道区（56）的源极轻掺杂区（58）和源极重掺杂区（60）。控制电极导电层（40）横向邻近侧壁电介质层（48），侧壁电介质层（48）横向邻近沟道区域（56）。导电层（40）用作晶体管（11）的栅电极。每个晶体管（10和11）是垂直集成的，例如在垂直集成的BiMOS电路中。晶体管（10和11）可通过隔离电隔离（64和66）。

4. 发明授权

US5376562A Method for forming vertical transistor structures having bipolar and MOS devices 失效
标题翻译：用于形成具有双极和MOS器件的垂直晶体管结构的方法
公开(公告)号：US5376562A
公开(公告)日：1994-12-27
申请号：US65419
申请日：1993-05-24
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek , James D. Hayden
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek , James D. Hayden
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/336 , H01L21/822 , H01L27/06 , H01L29/73 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66287 , H01L21/8221 , H01L27/0688 , H01L29/66666 , H01L29/6675 , H01L29/732 , H01L29/7827
摘要： A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).
摘要翻译：晶体管形成为双极晶体管（10）或MOS晶体管（11）。每个晶体管（10或11）具有衬底（12）。双极晶体管（10）具有位于控制电极（28）下方的第一电流电极（26）和覆盖控制电极（28）的第二电流电极（32）。 MOS晶体管（11）具有位于沟道区（56）下面的第一电流电极（54）和覆盖沟道区（56）的源极轻掺杂区（58）和源极重掺杂区（60）。控制电极导电层（40）横向邻近侧壁电介质层（48），侧壁电介质层（48）横向邻近沟道区域（56）。导电层（40）用作晶体管（11）的栅电极。每个晶体管（10和11）是垂直集成的，例如在垂直集成的BiMOS电路中。晶体管（10和11）可通过隔离电隔离（64和66）。

5. 发明授权

US5324673A Method of formation of vertical transistor 失效
标题翻译：垂直晶体管的形成方法
公开(公告)号：US5324673A
公开(公告)日：1994-06-28
申请号：US979073
申请日：1992-11-19
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
IPC分类号： H01L21/285 , H01L21/336 , H01L21/768 , H01L21/822 , H01L27/06 , H01L27/088 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66666 , H01L21/28525 , H01L21/76838 , H01L21/76885 , H01L21/8221 , H01L27/0688 , H01L27/088 , H01L29/6675 , H01L29/7827
摘要： A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.
摘要翻译：用于形成垂直晶体管（10）的方法通过提供衬底（12）开始。形成在衬底（12）上方的导电层（16）。通过选择性生长，外延生长，原位掺杂和/或离子注入之一，分别形成第一电流电极（26），第二电流电极（30）和沟道区（28）。栅极电极或控制电极（34）横向邻近沟道区（28）形成。使用选择性/外延生长步骤将导电层（16）连接到控制电极（34），并形成可靠且没有电流短路至电流电极（26和30）的控制电极互连。晶体管（10）可以垂直堆叠以形成紧凑的反相器电路。

6. 发明授权

US5256588A Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell 失效
标题翻译：用于形成用于垂直堆叠的动态随机存取存储单元的晶体管和电容器的方法
公开(公告)号：US5256588A
公开(公告)日：1993-10-26
申请号：US856411
申请日：1992-03-23
申请人： Keith E. Witek , Carlos A. Mazure , Jon T. Fitch
发明人： Keith E. Witek , Carlos A. Mazure , Jon T. Fitch
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A method for forming a transistor and a capacitor to provide, in one form, a DRAM cell (10). The capacitor of cell (10) is formed within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric.
摘要翻译：一种用于形成晶体管和电容器的方法，以一种形式提供DRAM单元（10）。电池（10）的电容器形成在衬底（12）内。电容器具有第一电容器电极（16）和第二电容器电极（20）。电介质层（18）形成为电极间电容器电介质。第一晶体管电流电极（36）被形成为覆盖并电连接到第一电容器电极（16）。沟道区（38）形成在第一晶体管电流电极（36）的上方。第二晶体管电流电极（40）形成在沟道区域（38）的上方。导电层（30）横向邻近沟道区（38）形成，并通过电介质层（22和28）与衬底（12）隔离。导电层（30）用作晶体管的栅电极，并且侧壁电介质（34）用作栅极电介质。

7. 发明授权

US5414289A Dynamic memory device having a vertical transistor 失效
标题翻译：具有垂直晶体管的动态存储器件
公开(公告)号：US5414289A
公开(公告)日：1995-05-09
申请号：US150328
申请日：1993-11-09
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L29/10 , H01L29/72
CPC分类号： H01L27/10876 , H01L21/823487 , H01L27/10808 , H01L27/10823 , H01L29/66666 , H01L29/7827 , H01L29/7834
摘要： A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).
摘要翻译：垂直晶体管（10）具有用作控制电极或栅电极的基板（12）和控制电极导电层（18）。侧壁电介质层（22）横向邻近控制电极导电层（18）形成并且覆盖在衬底（12）上。导电层（18）至少部分地围绕沟道区域（30）。在器件开口内形成垂直导电区域，其中导电区域的底部是第一电流电极（28）。垂直导电区域的中间部分是沟道区域（30）。垂直导电区域的顶部是第二电流电极（34）。

8. 发明授权

US5612563A Vertically stacked vertical transistors used to form vertical logic gate structures 失效
标题翻译：用于形成垂直逻辑门结构的垂直垂直晶体管
公开(公告)号：US5612563A
公开(公告)日：1997-03-18
申请号：US186872
申请日：1994-01-25
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
IPC分类号： H01L21/336 , H01L21/768 , H01L21/822 , H01L27/06 , H01L27/088 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66666 , H01L21/76897 , H01L21/8221 , H01L27/0688 , H01L27/088 , H01L29/6675 , H01L29/7827 , H01L29/7834
摘要： A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.
摘要翻译：晶体管（10）具有衬底（12）和扩散层（14）。栅极导电层（18）覆盖在衬底（12）上并且具有由暴露衬底（12）的开口形成的侧壁。在横向邻近导电层（18）侧壁形成的侧壁电介质层（22）用作晶体管（10）的栅极电介质。在开口内形成导电区域。导电区域具有第一电流电极区域（28）和第二控制电极区域（34）以及横向邻近侧壁电介质层（22）的沟道区域（30）。根据晶体管（10）的多个晶体管可以以垂直方式堆叠以形成诸如NMOS或PMOS NAND，NOR和反相门的逻辑门，和/或CMOS NAND，NOR和具有一个或多个输入。

9. 发明授权

US5340754A Method for forming a transistor having a dynamic connection between a substrate and a channel region 失效
标题翻译：用于形成在衬底和沟道区之间具有动态连接的晶体管的方法
公开(公告)号：US5340754A
公开(公告)日：1994-08-23
申请号：US940260
申请日：1992-09-02
申请人： Keith E. Witek , Jon T. Fitch , Carlos A. Mazure
发明人： Keith E. Witek , Jon T. Fitch , Carlos A. Mazure
IPC分类号： H01L21/336 , H01L27/06 , H01L27/118 , H01L29/417 , H01L29/735 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66666 , H01L27/0688 , H01L27/11807 , H01L29/41725 , H01L29/41766 , H01L29/41775 , H01L29/735 , H01L29/7827
摘要： A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.
摘要翻译：形成具有衬底（12）的垂直升高的晶体管（10）。导电插塞区域（22）被选择性地或外延地形成以垂直地提升晶体管（10）。第一掺杂区域（16a）和第二掺杂区域（16b）各自经由侧壁触点电耦合到导电插塞区域（22）。掺杂区域（16a和16b）用于在导电插塞区域（22）内形成电流电极区域（26）。沟道区域分离电流电极（26）。栅极电介质层（28）形成为覆盖沟道区域。形成导电层（30）以覆盖栅介电层（28）。导电层（30）形成晶体管（10）的栅电极。垂直升高晶体管（10）和导电插塞区域（22）提供改进的器件隔离和改进的器件操作。

10. 发明授权

US5308778A Method of formation of transistor and logic gates 失效
标题翻译：形成晶体管和逻辑门的方法
公开(公告)号：US5308778A
公开(公告)日：1994-05-03
申请号：US003813
申请日：1993-01-11
申请人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
发明人： Jon T. Fitch , Carlos A. Mazure , Keith E. Witek
IPC分类号： H01L27/00 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/70
CPC分类号： H01L29/66666 , H01L21/8221 , H01L27/0688 , H01L27/088 , H01L29/6675 , H01L29/7827 , H01L29/7834
摘要： A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with multiple inputs.
摘要翻译：晶体管（10）具有衬底（12）和扩散层（14）。栅极导电层（18）覆盖在衬底（12）上并且具有由暴露衬底（12）的开口形成的侧壁。在横向邻近导电层（18）侧壁形成的侧壁电介质层（22）用作晶体管（10）的栅极电介质。在开口内形成导电区域。导电区域具有第一电流电极区域（28）和第二控制电极区域（34）以及横向邻近侧壁电介质层（22）的沟道区域（30）。根据晶体管（10）的多个晶体管可以以垂直方式堆叠以形成诸如NMOS或PMOS NAND，NOR和反相门的逻辑门，和/或CMOS NAND，NOR和具有多个输入

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