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    • 2. 发明授权
    • Memory controller, data storage device, and memory controlling method
    • 内存控制器,数据存储设备和内存控制方式
    • US09191030B2
    • 2015-11-17
    • US13693360
    • 2012-12-04
    • Akihiro SakataYoshinobu Kimura
    • Akihiro SakataYoshinobu Kimura
    • H03M13/29G06F11/10
    • H03M13/29G06F11/1004H03M13/2906
    • A memory controller includes a first error detection code generator for generating a first error detection code for data received from a host, a controller to write the data and the first error detection code to nonvolatile memory and to read the data and the first error detection code from the nonvolatile memory, an error detector to perform an error detection based on the data and the first error detection code that are read from the nonvolatile memory, a second error detection code generator to generate a second detection error code based on the data read from the nonvolatile memory, and a mismatch code generator to generate a mismatch code signaling the presence of an error in the data, wherein either the second error detection code or the mismatch code is selected based on the error detection and sent to the host.
    • 存储器控制器包括:第一错误检测码发生器,用于产生用于从主机接收的数据的第一错误检测码,控制器将数据和第一错误检测码写入非易失性存储器,并读取数据和第一错误检测码 来自所述非易失性存储器的误差检测器,基于从所述非易失性存储器读取的所述数据和所述第一检错码执行错误检测;第二检错码发生器,用于基于从所述非易失性存储器读取的数据产生第二检测错误代码; 所述非易失性存储器和不匹配码发生器产生用于发信号通知所述数据中存在错误的不匹配码,其中所述第二错误检测码或所述不匹配码是基于所述错误检测被选择的并被发送给所述主机。