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1. 发明申请

US20080201672A1 CASCADED PASS-GATE TEST CIRCUIT WITH INTERPOSED SPLIT-OUTPUT DRIVE DEVICES 失效
标题翻译：带插入式分接输出驱动器件的嵌入式门电路测试电路
公开(公告)号：US20080201672A1
公开(公告)日：2008-08-21
申请号：US11762257
申请日：2007-06-13
申请人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
发明人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
IPC分类号： G06F17/50
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

2. 发明授权

US07782092B2 Cascaded pass-gate test circuit with interposed split-output drive devices 失效
标题翻译：带有插入式分离输出驱动装置的级联传输门测试电路
公开(公告)号：US07782092B2
公开(公告)日：2010-08-24
申请号：US11762257
申请日：2007-06-13
申请人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
发明人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
IPC分类号： H03K19/094
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

3. 发明授权

US07323908B2 Cascaded pass-gate test circuit with interposed split-output drive devices 失效
标题翻译：带有插入式分离输出驱动装置的级联传输门测试电路
公开(公告)号：US07323908B2
公开(公告)日：2008-01-29
申请号：US11260571
申请日：2005-10-27
申请人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
发明人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
IPC分类号： H03K19/0175 , H03K19/094 , H03K3/03
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

4. 发明授权

US07298176B2 Dual-gate dynamic logic circuit with pre-charge keeper 有权
标题翻译：双栅极动态逻辑电路，带有预充电保护器
公开(公告)号：US07298176B2
公开(公告)日：2007-11-20
申请号：US11204401
申请日：2005-08-16
申请人： Hung C. Ngo , Ching-Te Chuang , Keunwoo Kim , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Ching-Te Chuang , Keunwoo Kim , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/20
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.
摘要翻译：动态逻辑门具有非对称双栅极PFET器件，用于在时钟的预充电阶段期间对动态节点进行充电。逻辑树在时钟的评估阶段评估动态节点。非对称双栅极PFET器件的前栅极耦合到时钟信号，而后栅极耦合到电源的地电位。当时钟为逻辑0时，前门和后门都被偏置为ON，动态节点以最大电流充电。在时钟关断前门的评估阶段，时钟信号转变为逻辑1。背栅保持接通，并且非对称双栅极PFET器件作为具有足以抵抗动态节点上的泄漏的电流水平的保持器器件工作。

5. 发明授权

US07719315B2 Programmable local clock buffer 失效
标题翻译：可编程本地时钟缓冲器
公开(公告)号：US07719315B2
公开(公告)日：2010-05-18
申请号：US11554666
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译：可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。扫描时钟前馈电路接收本地时钟并产生扫描时钟。数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

6. 发明申请

US20080100360A1 PULSED LOCAL CLOCK BUFFER (LCB) CHARACTERIZATION RING OSCILLATOR 失效
标题翻译：脉冲本地时钟缓冲器（LCB）特征振荡器
公开(公告)号：US20080100360A1
公开(公告)日：2008-05-01
申请号：US11553014
申请日：2006-10-26
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G01R31/31727 , G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K5/156
摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.
摘要翻译：在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。输出驱动器输出脉宽调整信号。脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

7. 发明授权

US06975134B2 Buffer/driver circuits 失效
标题翻译：缓冲/驱动电路
公开(公告)号：US06975134B2
公开(公告)日：2005-12-13
申请号：US10821048
申请日：2004-04-08
申请人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/0016 , H03K19/01721
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译：具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。

8. 发明申请

US20120212997A1 TEST STRUCTURE FOR CHARACTERIZING MULTI-PORT STATIC RANDOM ACCESS MEMORY AND REGISTER FILE ARRAYS 失效
标题翻译：表征多端口静态随机访问存储器和寄存器文件阵列的测试结构
公开(公告)号：US20120212997A1
公开(公告)日：2012-08-23
申请号：US13459932
申请日：2012-04-30
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

9. 发明申请

US20080155362A1 Test Structure for Characterizing Multi-Port Static Random Access Memory and Register File Arrays 有权
标题翻译：用于表征多端口静态随机存取存储器和寄存器文件数组的测试结构
公开(公告)号：US20080155362A1
公开(公告)日：2008-06-26
申请号：US11552158
申请日：2006-10-24
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

10. 发明申请

US20080101522A1 Programmable Local Clock Buffer 失效
标题翻译：可编程本地时钟缓冲器
公开(公告)号：US20080101522A1
公开(公告)日：2008-05-01
申请号：US11554666
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译：可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。延迟控制信号反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。扫描时钟前馈电路接收本地时钟并产生扫描时钟。数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

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