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1. 发明授权

US08647953B2 Method for fabricating first and second epitaxial cap layers 有权
标题翻译：用于制造第一和第二外延盖层的方法
公开(公告)号：US08647953B2
公开(公告)日：2014-02-11
申请号：US13299044
申请日：2011-11-17
申请人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
摘要翻译：描述了一种用于制造金属氧化物半导体（MOS）器件的方法，包括以下步骤。在基板上形成两个凹部。进行第一外延生长工艺，以在每个凹部中形成第一半导体化合物层。在外延温度低于700℃的条件下进行第二外延生长工艺，以便在每个第一半导体化合物层上形成覆盖层。每个盖层包括从基板的表面突出的第二半导体化合物层。第一和第二半导体化合物层由第一IV族元素和第二种IV族元素组成，其中第二族IV元素是非硅元素。第二半导体化合物层中的第二IV族元素的含量小于第一半导体化合物层中的含量。

2. 发明申请

US20130126949A1 MOS DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译： MOS器件及其制造方法
公开(公告)号：US20130126949A1
公开(公告)日：2013-05-23
申请号：US13299044
申请日：2011-11-17
申请人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/823814 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
摘要翻译：描述了一种用于制造金属氧化物半导体（MOS）器件的方法，包括以下步骤。在基板上形成两个凹部。进行第一外延生长工艺，以便在每个凹部中形成第一半导体化合物层。在外延温度低于700℃的条件下进行第二外延生长工艺，以便在每个第一半导体化合物层上形成覆盖层。每个盖层包括从基板的表面突出的第二半导体化合物层。第一和第二半导体化合物层由第一IV族元素和第二种IV族元素组成，其中第二族IV元素是非硅元素。第二半导体化合物层中的第二IV族元素的含量小于第一半导体化合物层中的含量。

3. 发明授权

US08962433B2 MOS transistor process 有权
标题翻译： MOS晶体管工艺
公开(公告)号：US08962433B2
公开(公告)日：2015-02-24
申请号：US13494016
申请日：2012-06-12
申请人： Chin-I Liao , Chin-Cheng Chien
发明人： Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/4966 , H01L29/66636 , H01L29/7848
摘要： A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.
摘要翻译： MOS晶体管工艺包括以下步骤。在基板上形成栅极结构。在栅极结构旁边的衬底中形成源极/漏极。在形成源极/漏极之后，（1）在栅极结构旁边的基板中形成至少一个凹部。在凹部中形成外延结构。（2）可以进行清洁处理以清洁栅极结构旁边的基板的表面。在栅极结构旁边的衬底中形成外延结构。

4. 发明授权

US08921206B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08921206B2
公开(公告)日：2014-12-30
申请号：US13308513
申请日：2011-11-30
申请人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
发明人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/36
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.
摘要翻译：首先，在半导体工艺中设置具有凹部的基板。第二，在衬底中形成嵌入的SiGe层。嵌入的SiGe层包括填充凹槽的外延SiGe材料。然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

5. 发明授权

US08716750B2 Semiconductor device having epitaxial structures 有权
标题翻译：具有外延结构的半导体器件
公开(公告)号：US08716750B2
公开(公告)日：2014-05-06
申请号：US13189570
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.
摘要翻译：具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。外延结构包括掺杂剂，具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料，并且第二晶格常数大于第一晶格常数。未掺杂的帽层还包括第一半导体材料和第二半导体材料。外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料至少包含第一浓度，第二浓度低于第一浓度。

6. 发明授权

US08519390B2 Test pattern for measuring semiconductor alloys using X-ray Diffraction 有权
$Test pattern for measuring semiconductor alloys using X-ray Diffraction$
标题翻译：使用X射线衍射测量半导体合金的测试图案
公开(公告)号：US08519390B2
公开(公告)日：2013-08-27
申请号：US13189565
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L23/58
CPC分类号： H01L22/12 , H01L22/30
摘要： A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.
摘要翻译：使用X射线衍射（XRD）测量半导体合金的测试图案包括限定在晶片上的第N个区域和第N个区域，以及位于第一区域等等至第N区域的多个测试结构。相同区域中的测试结构具有彼此相同的尺寸，并且不同区域中的测试结构具有彼此不同的尺寸。

7. 发明授权

US08481391B2 Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure 有权
标题翻译：制造应力提供结构的工艺和具有这种应力提供结构的半导体器件
公开(公告)号：US08481391B2
公开(公告)日：2013-07-09
申请号：US13110294
申请日：2011-05-18
申请人： Chin-I Liao , Ching-Hong Jiang , Ching-I Li , Shu-Yen Chan , Chin-Cheng Chien
发明人： Chin-I Liao , Ching-Hong Jiang , Ching-I Li , Shu-Yen Chan , Chin-Cheng Chien
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/3247 , H01L29/66636 , H01L29/7848
摘要： A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.
摘要翻译：制造应力提供结构的方法被应用于半导体器件的制造。首先，提供具有沟道结构的衬底。通过化学气相沉积在含卤素的环境中在衬底上形成氮化硅层。执行蚀刻处理以部分地去除氮化硅层以暴露基板的表面的一部分在通道结构旁边。蚀刻衬底的暴露表面以在衬底中形成凹陷。然后，将衬底在750℃和820℃之间的温度下进行热处理。在对衬底进行热处理之后，在凹部中填充应力提供材料，以在凹部内形成应力提供结构。半导体器件包括衬底，凹部和应力提供结构。凹槽具有圆形的内表面。应力提供结构具有圆形外表面。

8. 发明申请

US20100093147A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20100093147A1
公开(公告)日：2010-04-15
申请号：US12251438
申请日：2008-10-14
申请人： Chin-I Liao , Chin-Cheng Chien
发明人： Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28123 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a substrate having at least a gate positioned thereon, forming at least a recess in the substrate adjacent to the gate, performing a first selective epitaxial growth (SEG) process to form a first epitaxial layer in the recess, performing an etching process to remove a portion of the first epitaxial layer to expose the substrate, and performing a second SEG process to form a second epitaxial layer on the first epitaxial layer.
摘要翻译：一种用于形成半导体器件的方法包括：提供至少具有栅极的衬底，至少在衬底中形成与栅极相邻的凹槽，执行第一选择性外延生长（SEG）工艺以形成第一外延层凹陷，执行蚀刻工艺以去除第一外延层的一部分以露出衬底，以及执行第二SEG工艺以在第一外延层上形成第二外延层。

9. 发明授权

US08664069B2 Semiconductor structure and process thereof 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US08664069B2
公开(公告)日：2014-03-04
申请号：US13440978
申请日：2012-04-05
申请人： Chin-I Liao , Chin-Cheng Chien
发明人： Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L29/66628 , H01L29/66636
摘要： A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.
摘要翻译：半导体结构包括栅极结构，外延层和含碳硅锗覆盖层。栅极结构位于衬底上。外延层位于栅极结构旁边的衬底中。含碳硅锗覆盖层位于外延层上。否则，还提供了用于形成所述半导体结构的半导体工艺。

10. 发明申请

US20130092954A1 Strained Silicon Channel Semiconductor Structure and Method of Making the Same 有权
标题翻译：应变硅通道半导体结构及其制作方法
公开(公告)号：US20130092954A1
公开(公告)日：2013-04-18
申请号：US13274357
申请日：2011-10-17
申请人： Chan-Lon Yang , Ted Ming-Lang Guo , Chin-I Liao , Chin-Cheng Chien , Shu-Yen Chan , Chun-Yuan Wu
发明人： Chan-Lon Yang , Ted Ming-Lang Guo , Chin-I Liao , Chin-Cheng Chien , Shu-Yen Chan , Chun-Yuan Wu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/04
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3247 , H01L21/823425 , H01L29/6656 , H01L29/66636
摘要： A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.
摘要翻译：一种制造应变通道半导体结构的方法包括提供衬底，在所述衬底上形成至少一个栅极结构，执行蚀刻工艺以在所述衬底的所述栅极结构的相对侧形成两个凹槽，所述凹槽的侧壁为凹面在所述栅极结构的方向上并相对于水平面形成夹角，并且执行预烘烤处理以改变凹部，使得所述凹部的侧壁和水平面之间的所述夹角增加。

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