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1. 发明授权

US08647953B2 Method for fabricating first and second epitaxial cap layers 有权
标题翻译：用于制造第一和第二外延盖层的方法
公开(公告)号：US08647953B2
公开(公告)日：2014-02-11
申请号：US13299044
申请日：2011-11-17
申请人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
摘要翻译：描述了一种用于制造金属氧化物半导体（MOS）器件的方法，包括以下步骤。在基板上形成两个凹部。进行第一外延生长工艺，以在每个凹部中形成第一半导体化合物层。在外延温度低于700℃的条件下进行第二外延生长工艺，以便在每个第一半导体化合物层上形成覆盖层。每个盖层包括从基板的表面突出的第二半导体化合物层。第一和第二半导体化合物层由第一IV族元素和第二种IV族元素组成，其中第二族IV元素是非硅元素。第二半导体化合物层中的第二IV族元素的含量小于第一半导体化合物层中的含量。

2. 发明申请

US20130126949A1 MOS DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译： MOS器件及其制造方法
公开(公告)号：US20130126949A1
公开(公告)日：2013-05-23
申请号：US13299044
申请日：2011-11-17
申请人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/823814 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L29/045 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
摘要翻译：描述了一种用于制造金属氧化物半导体（MOS）器件的方法，包括以下步骤。在基板上形成两个凹部。进行第一外延生长工艺，以便在每个凹部中形成第一半导体化合物层。在外延温度低于700℃的条件下进行第二外延生长工艺，以便在每个第一半导体化合物层上形成覆盖层。每个盖层包括从基板的表面突出的第二半导体化合物层。第一和第二半导体化合物层由第一IV族元素和第二种IV族元素组成，其中第二族IV元素是非硅元素。第二半导体化合物层中的第二IV族元素的含量小于第一半导体化合物层中的含量。

3. 发明申请

US20140070377A1 COMPOUND SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：化合物半导体外延结构及其制备方法
公开(公告)号：US20140070377A1
公开(公告)日：2014-03-13
申请号：US13606007
申请日：2012-09-07
申请人： Tien-Wei YU , Chin-Cheng CHIEN , I-Ming LAI , Shin-Chi CHEN , Chih-Yueh LI , Fong-Lung CHUANG , Chin-I LIAO , Kuan-Yu LIN
发明人： Tien-Wei YU , Chin-Cheng CHIEN , I-Ming LAI , Shin-Chi CHEN , Chih-Yueh LI , Fong-Lung CHUANG , Chin-I LIAO , Kuan-Yu LIN
IPC分类号： C30B25/14 , H01L29/36
CPC分类号： H01L21/02639 , C30B25/165 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.
摘要翻译：一种制备化合物半导体外延结构的方法包括以下步骤。首先，在基板上形成第一复合外延层。然后，进行连续的外延沉积工艺以在第一复合外延层上形成第二化合物外延层，使得第二化合物外延层具有线性降低的金属浓度梯度。之后，在第二复合外延层上形成半导体材料层。

4. 发明授权

US08710632B2 Compound semiconductor epitaxial structure and method for fabricating the same 有权
标题翻译：化合物半导体外延结构及其制造方法
公开(公告)号：US08710632B2
公开(公告)日：2014-04-29
申请号：US13606007
申请日：2012-09-07
申请人： Tien-Wei Yu , Chin-Cheng Chien , I-Ming Lai , Shin-Chi Chen , Chih-Yueh Li , Fong-Lung Chuang , Chin-I Liao , Kuan-Yu Lin
发明人： Tien-Wei Yu , Chin-Cheng Chien , I-Ming Lai , Shin-Chi Chen , Chih-Yueh Li , Fong-Lung Chuang , Chin-I Liao , Kuan-Yu Lin
IPC分类号： H01L21/02
CPC分类号： H01L21/02639 , C30B25/165 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.
摘要翻译：一种制备化合物半导体外延结构的方法包括以下步骤。首先，在基板上形成第一复合外延层。然后，进行连续的外延沉积工艺以在第一复合外延层上形成第二化合物外延层，使得第二化合物外延层具有线性降低的金属浓度梯度。之后，在第二复合外延层上形成半导体材料层。

5. 发明申请

US20130137243A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130137243A1
公开(公告)日：2013-05-30
申请号：US13308513
申请日：2011-11-30
申请人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
发明人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/20
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.
摘要翻译：首先，在半导体工艺中设置具有凹部的基板。第二，在衬底中形成嵌入的SiGe层。嵌入的SiGe层包括填充凹槽的外延SiGe材料。然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

6. 发明授权

US08445363B2 Method of fabricating an epitaxial layer 有权
标题翻译：制造外延层的方法
公开(公告)号：US08445363B2
公开(公告)日：2013-05-21
申请号：US13091153
申请日：2011-04-21
申请人： Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
发明人： Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
IPC分类号： H01L21/20
CPC分类号： H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要： A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
摘要翻译：制造外延层的方法包括提供衬底。衬底被蚀刻以在衬底内形成至少一个凹部。在凹部上进行表面处理以形成含Si-OH的表面。进行原位外延工艺以在凹槽内形成外延层，其中外延工艺在无氢气氛和低于800℃的温度下进行。

7. 发明申请

US20130026464A1 TEST PATTERN FOR MEASURING SEMICONDUCTOR ALLOYS USING X-RAY DIFFRACTION 有权
标题翻译：使用X射线衍射测量半导体合金的测试图案
公开(公告)号：US20130026464A1
公开(公告)日：2013-01-31
申请号：US13189565
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L23/544
CPC分类号： H01L22/12 , H01L22/30
摘要： A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.
摘要翻译：使用X射线衍射（XRD）测量半导体合金的测试图案包括限定在晶片上的第N个区域和第N个区域，以及位于第一区域等等至第N区域的多个测试结构。相同区域中的测试结构具有彼此相同的尺寸，并且不同区域中的测试结构具有彼此不同的尺寸。

8. 发明申请

US20120270382A1 METHOD OF FABRICATING AN EPITAXIAL LAYER 有权
标题翻译：制作外延层的方法
公开(公告)号：US20120270382A1
公开(公告)日：2012-10-25
申请号：US13091153
申请日：2011-04-21
申请人： Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
发明人： Tsuo-Wen Lu , I-Ming Lai , Tsung-Yu Hou , Chien-Liang Lin , Wen-Yi Teng , Shao-Wei Wang , Yu-Ren Wang , Chin-Cheng Chien
IPC分类号： H01L21/20
CPC分类号： H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02658 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要： A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.
摘要翻译：制造外延层的方法包括提供衬底。衬底被蚀刻以在衬底内形成至少一个凹部。在凹部上进行表面处理以形成含Si-OH表面。进行原位外延工艺以在凹槽内形成外延层，其中外延工艺在无氢气氛和低于800℃的温度下进行。

9. 发明申请

US20130026538A1 SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES 有权
标题翻译：具有外延结构的半导体器件
公开(公告)号：US20130026538A1
公开(公告)日：2013-01-31
申请号：US13189570
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L29/165 , H01L29/78
CPC分类号： H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.
摘要翻译：具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。外延结构包括掺杂剂，具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料，并且第二晶格常数大于第一晶格常数。未掺杂的帽层还包括第一半导体材料和第二半导体材料。外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料至少包含第一浓度，第二浓度低于第一浓度。

10. 发明授权

US08921206B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08921206B2
公开(公告)日：2014-12-30
申请号：US13308513
申请日：2011-11-30
申请人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
发明人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/36
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.
摘要翻译：首先，在半导体工艺中设置具有凹部的基板。第二，在衬底中形成嵌入的SiGe层。嵌入的SiGe层包括填充凹槽的外延SiGe材料。然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

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