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1. 发明申请

US20070278424A1 METHOD AND APPARATUS TO IMPROVE LITHOGRAPHY THROUGHPUT 有权
标题翻译：改进算法的方法和装置
公开(公告)号：US20070278424A1
公开(公告)日：2007-12-06
申请号：US11421590
申请日：2006-06-01
申请人： Chin-Hsiang LIN , Jui-Chung PENG , Yung-Cheng CHEN , Shy-Jan LIN
发明人： Chin-Hsiang LIN , Jui-Chung PENG , Yung-Cheng CHEN , Shy-Jan LIN
IPC分类号： G03F7/20
CPC分类号： G03F7/70991 , G03F7/70466
摘要： The present disclosure provides a lithography apparatus with improved lithography throughput. The lithography apparatus includes a first lens system; a first substrate stage configured to receive a first radiation energy from the first lens system, and designed operable to move a substrate during an exposing process; a second lens system, having a higher resolution than that of the first lens system; and a second substrate stage approximate to the first substrate stage and configured to receive a second radiation energy from the second lens system, and designed operable to receive the substrate from the first substrate stage and move the substrate.
摘要翻译：本公开提供了具有改进的光刻产量的光刻设备。光刻设备包括第一透镜系统; 第一衬底台，被配置为从所述第一透镜系统接收第一辐射能量，并且被设计为可操作以在曝光过程期间移动衬底; 第二透镜系统，具有比第一透镜系统更高的分辨率; 以及第二衬底台，其近似于所述第一衬底台并且被配置为从所述第二透镜系统接收第二辐射能量，并且被设计为可操作以从所述第一衬底台接收所述衬底并移动所述衬底。

2. 发明申请

US20110083496A1 SEMICONDUCTOR PROCESSING APPARATUS WITH SIMULTANEOUSLY MOVABLE STAGES 有权
标题翻译：半导体加工设备与同时可移动的阶段
公开(公告)号：US20110083496A1
公开(公告)日：2011-04-14
申请号：US12576526
申请日：2009-10-09
申请人： Yu-Fu LIN , Yung-Cheng CHEN , Heng-Jen LEE , Chin-Hsiang LIN
发明人： Yu-Fu LIN , Yung-Cheng CHEN , Heng-Jen LEE , Chin-Hsiang LIN
IPC分类号： G01N33/00 , G01N21/55 , G03B27/52
CPC分类号： H01L21/68785 , B82Y10/00 , B82Y40/00 , G03F7/70525 , G03F7/70725 , G03F7/70733 , G03F7/70766 , H01J37/3174 , H01L21/68
摘要： A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other.
摘要翻译：一种方法和装置提供同时在相反方向上移动多个半导体晶片，同时对每个晶片执行处理操作。半导体晶片以共面方式取向，并且设置在同时沿相反方向平移的阶段上，以产生零的系统动量。相对于半导体晶片的全局对准特征，对相应的半导体晶片的管芯进行相同的空间序列处理。不需要平衡质量来抵消舞台的运动，因为各个舞台的相反运动彼此抵消。

3. 发明申请

US20130309612A1 ENHANCED SCANNER THROUGHPUT SYSTEM AND METHOD 有权
标题翻译：增强扫描仪通过系统和方法
公开(公告)号：US20130309612A1
公开(公告)日：2013-11-21
申请号：US13473695
申请日：2012-05-17
申请人： Yu-Mei LIU , Chin-Hsiang LIN , Heng-Hsin LIU , Heng-Jen LEE , I-Hsiung HUANG , Chih-Wei LIN
发明人： Yu-Mei LIU , Chin-Hsiang LIN , Heng-Hsin LIU , Heng-Jen LEE , I-Hsiung HUANG , Chih-Wei LIN
IPC分类号： G03F7/20
CPC分类号： G03F7/70358
摘要： A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.
摘要翻译：提供了一种提高扫描仪吞吐量的方法和系统。使用连续线性扫描程序将来自掩模版的图像投影到基板上，其中连续扫描整列管芯或裸片的单元，即不进入不同的位置。每个扫描包括相对于固定光束平移衬底。当底物被翻译时，掩模版也被翻译。当模具的第一裸片或裸片投影到衬底上时，标线沿着与扫描方向相反的方向平移，并且随着扫描沿着相同的方向继续，标线片然后在衬底的相反方向上平移，从而形成倒置图案在下一个死亡或细胞。与曝光底物相关的时间最小化，因为步进操作仅在扫描完整的单元格列之后才发生。

4. 发明申请

US20120086075A1 DEVICE WITH ALUMINUM SURFACE PROTECTION 有权
标题翻译：具有铝表面保护的器件
公开(公告)号：US20120086075A1
公开(公告)日：2012-04-12
申请号：US13327992
申请日：2011-12-16
申请人： Kuo Bin HUANG , Ssu-Yi LI , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
发明人： Kuo Bin HUANG , Ssu-Yi LI , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
IPC分类号： H01L27/088
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/28247 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.
摘要翻译：具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及在第一金属层上的第一铝层。第一铝层包括包含铝，氮和氧的界面层。该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数，和在第二金属层上的第二铝层。

5. 发明申请

US20120064715A1 INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION 有权
标题翻译：底部金属膜沉积的整合
公开(公告)号：US20120064715A1
公开(公告)日：2012-03-15
申请号：US13302520
申请日：2011-11-22
申请人： Simon Su-Horng LIN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
发明人： Simon Su-Horng LIN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
IPC分类号： H01L21/26
CPC分类号： H01L29/78 , C23C14/022 , C23C14/046 , C23C14/18 , C23C14/221 , C23C16/0263 , C23C16/045 , C23C16/06 , C23C16/48 , C23C16/484 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L21/76865 , H01L21/76877 , H01L29/4966 , H01L29/66545
摘要： A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.
摘要翻译：在具有图案特征的基板上沉积金属膜的方法包括将具有图案化特征的基板放置在光致化学气相沉积（PI-CVD）处理室中。该方法还包括通过PI-CVD沉积金属膜以从下向上填充图案化特征。

6. 发明申请

US20120045192A1 SYSTEM AND METHOD FOR IMPROVING IMMERSION SCANNER OVERLAY PERFORMANCE 有权
标题翻译：改进扫描仪覆盖性能的系统和方法
公开(公告)号：US20120045192A1
公开(公告)日：2012-02-23
申请号：US13288133
申请日：2011-11-03
申请人： Jui-Cheng PENG , Tzung-Chi FU , Chin-Hsiang LIN , Chien-Hsun LIN , Chun-Hung LIN , Yao-Wen GUO , Shy-Jay LIN , Heng-Hsin LIU
发明人： Jui-Cheng PENG , Tzung-Chi FU , Chin-Hsiang LIN , Chien-Hsun LIN , Chun-Hung LIN , Yao-Wen GUO , Shy-Jay LIN , Heng-Hsin LIU
IPC分类号： G03B29/00
CPC分类号： G03F7/70875 , G03F7/70341 , G03F7/70783
摘要： System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner comprising a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method comprises providing a water tank at at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level.
摘要翻译：描述了用于提高浸没式扫描仪覆盖性能的系统和方法。一个实施例是一种提高光刻浸没式扫描仪的覆盖性能的方法，其包括设置在其中的水通道中的透镜冷却水（“LCW”）的晶片台，晶片台具有用于将LCW接收到水通道中的输入端，输出用于从水道排出LCW。该方法包括在晶片台输入和晶片台输出中的至少一个上提供水箱; 监测水箱内的水压; 并且将水箱中的水的压力保持在预定水平。

7. 发明申请

US20080030692A1 NOVEL PHOTORESIST MATERIALS AND PHOTOLITHOGRAPHY PROCESS 有权
标题翻译：新型光电材料和光刻方法
公开(公告)号：US20080030692A1
公开(公告)日：2008-02-07
申请号：US11462413
申请日：2006-08-04
申请人： Hsien-Cheng WANG , Chin-Hsiang LIN , H. J. LEE , Ching-Yu CHANG , Hua-Tai LIN , Burn Jeng LIN
发明人： Hsien-Cheng WANG , Chin-Hsiang LIN , H. J. LEE , Ching-Yu CHANG , Hua-Tai LIN , Burn Jeng LIN
IPC分类号： G03F7/26
CPC分类号： G03F7/0397 , G03F7/0045 , G03F7/0392 , G03F7/30 , G03F7/38 , G03F7/70858 , Y10S430/106 , Y10S430/111
摘要： A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.
摘要翻译：用于光刻处理的材料包括响应于与酸的反应而变成可溶于碱溶液的聚合物和多个具有磁性元素的磁放大发生器（MAG），并分别与磁性元件形成酸结合响应辐射能量。

8. 发明申请

US20070224795A1 DUMMY VIAS FOR DAMASCENE PROCESS 有权
标题翻译： DAMASCENE过程的DUMMY VIAS
公开(公告)号：US20070224795A1
公开(公告)日：2007-09-27
申请号：US11457032
申请日：2006-07-12
申请人： Kuei Shun CHEN , Chin-Hsiang LIN , Vencent CHANG , Lawrence LIN , Lai Chien WEN , Jhun Hua CHEN
发明人： Kuei Shun CHEN , Chin-Hsiang LIN , Vencent CHANG , Lawrence LIN , Lai Chien WEN , Jhun Hua CHEN
IPC分类号： H01L21/44
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76813 , H01L21/7684 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).
摘要翻译：制造集成电路的方法包括在衬底上提供低k电介质层，低k电介质层包括或邻近多个导电特征; 图案化低k电介质层以形成沟槽; 图案化低k电介质层以形成导电通孔和虚拟通孔，其中每个导电通孔与多个导电特征中的至少一个对齐，并且至少一个沟槽，并且每个虚拟通孔是在多个导电特征之上的距离; 使用一种或多种导电材料填充沟槽，导电通孔和虚拟通孔; 并平坦化导电材料。

9. 发明申请

US20070091287A1 IMMERSION LITHOGRAPHY APPARATUS AND METHODS 有权
标题翻译：倾斜平面设备和方法
公开(公告)号：US20070091287A1
公开(公告)日：2007-04-26
申请号：US11427421
申请日：2006-06-29
申请人： Ching-Yu CHANG , Burn Jeng LIN , Chin-Hsiang LIN
发明人： Ching-Yu CHANG , Burn Jeng LIN , Chin-Hsiang LIN
IPC分类号： B08B3/12 , B08B7/00 , B08B3/00 , G03B27/52
CPC分类号： G03F7/70925 , G03F7/70341
摘要： A lithography apparatus includes an imaging lens module; a substrate table positioned underlying the imaging lens module and configured to hold a substrate; and a cleaning module adapted to clean the lithography apparatus. The cleaning module is selected from the group consisting of an ultrasonic unit, a scrubber, a fluid jet, an electrostatic cleaner, and combinations thereof.
摘要翻译：光刻设备包括成像透镜模块; 位于所述成像透镜模块下方且被配置为保持基板的基板台; 以及适于清洁光刻设备的清洁模块。清洁模块选自超声波单元，洗涤器，流体射流，静电清洁器及其组合。

10. 发明申请

US20130295297A1 SEMICONDUCTOR FILM FORMATION APPARATUS AND PROCESS 有权
标题翻译：半导体膜形成装置和工艺
公开(公告)号：US20130295297A1
公开(公告)日：2013-11-07
申请号：US13460884
申请日：2012-05-01
申请人： You-Hua CHOU , Chih-Tsung LEE , Shu-Fen WU , Chin-Hsiang LIN
发明人： You-Hua CHOU , Chih-Tsung LEE , Shu-Fen WU , Chin-Hsiang LIN
IPC分类号： C23C16/455 , H05H1/24
CPC分类号： C23C16/45565 , C23C16/5096
摘要： An apparatus and method are disclosed for forming thin films on a semiconductor substrate. The apparatus in one embodiment includes a process chamber configured for supporting the substrate, a gas excitation power source, and first and second gas distribution showerheads fluidly coupled to a reactive process gas supply containing film precursors. The showerheads dispense the gas into two different zones above the substrate, which is excited to generate an inner plasma field and an outer plasma field over the wafer. The apparatus deposits a material on the substrate in a manner that promotes the formation of a film having a substantially uniform thickness across the substrate. In one embodiment, the substrate is a wafer. Various embodiments include first and second independently controllable power sources connected to the first and second showerheads to vary the power level and plasma intensity in each zone.
摘要翻译：公开了用于在半导体衬底上形成薄膜的装置和方法。在一个实施例中的装置包括被配置用于支撑衬底，气体激发电源以及流体耦合到含有反应性工艺气体源的膜前体的第一和第二气体分配喷头的处理室。喷头将气体分配到衬底上方的两个不同区域中，该衬底被激发以在晶片上产生内部等离子体场和外部等离子体场。该装置以促进在基底上形成具有基本上均匀的厚度的膜的方式将材料沉积在基底上。在一个实施例中，衬底是晶片。各种实施例包括连接到第一和第二喷头的第一和第二可独立控制的电源，以改变每个区域中的功率电平和等离子体强度。

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