专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06884736B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US06884736B2
公开(公告)日：2005-04-26
申请号：US10265937
申请日：2002-10-07
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法。半导体元件形成在基板上。半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。然后用导电材料填充接触开口以形成接触。

2. 发明授权

US08110890B2 Method of fabricating semiconductor device isolation structure 有权
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US08110890B2
公开(公告)日：2012-02-07
申请号：US11758043
申请日：2007-06-05
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L21/70
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

3. 发明申请

US20080194087A1 Polysilicon gate formation by in-situ doping 有权
公开(公告)号：US20080194087A1
公开(公告)日：2008-08-14
申请号：US11729009
申请日：2007-03-28
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L21/3205 , H01L21/22 , H01L21/38
CPC分类号： H01L29/7834 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

4. 发明申请

US20080194072A1 Polysilicon gate formation by in-situ doping 审中-公开
标题翻译：通过原位掺杂形成多晶硅栅
公开(公告)号：US20080194072A1
公开(公告)日：2008-08-14
申请号：US11705655
申请日：2007-02-12
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/82345 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

5. 发明授权

US06365523B1 Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers 有权
标题翻译：集成高密度等离子体化学气相沉积（HDP-CVD）方法和用于形成图案化平面化孔径填充层的化学机械抛光（CMP）平面化方法
公开(公告)号：US06365523B1
公开(公告)日：2002-04-02
申请号：US09177188
申请日：1998-10-22
申请人： Syun-Ming Jang , Chu-Yun Fu , Ying-Ho Chen
发明人： Syun-Ming Jang , Chu-Yun Fu , Ying-Ho Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31612
摘要： A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method. The blanket first aperture fill layer fills the series of apertures to a planarizing thickness at least as high as the height of the mesas while simultaneously forming a series of protrusions of the blanket first aperture fill layer corresponding with the series of mesas, where the thickness of a protrusion of the blanket first aperture fill layer over a narrow mesa is less than the thickness of a protrusion of the blanket first aperture fill layer over a wide mesa. The first simultaneous deposition and sputter method employs a first deposition rate:sputter rate ratio which provides sufficient thickness of the blanket first aperture fill layer over the narrow mesa such that upon chemical mechanical polish (CMP) planarizing the blanket first aperture fill layer to form a series of patterned planarized first aperture fill layers within the series of apertures erosion of the narrow mesa is attenuated. Finally, there is then chemical mechanical polish (CMP) planarized the blanket first aperture fill layer to form the series of patterned planarized first aperture fill layers within the series of apertures.
摘要翻译：一种用于在微电子学制造中使用的地形衬底层内的一系列孔内形成一系列图案化的平坦化孔填充层的方法。首先提供了在微电子制造中使用的地形衬底层，其中地形衬底层包括基本上等同的高度但具有不同宽度的一系列台面，并且一系列台面由一系列孔分隔开。然后在地形衬底层上形成毯子第一孔填充层。毯子第一孔填充层使用第一同时沉积和溅射方法形成。毯子第一孔填充层将一系列孔填充至至少与台面的高度相同的平坦化厚度，同时形成与一系列台面相对应的毯子第一孔填充层的一系列突起，其中厚度毯子第一孔填充层在窄台面上的突起小于宽台面上的第一孔填充层的突起的厚度。第一同时沉积和溅射方法使用第一沉积速率：溅射速率比，其在窄台面上提供足够厚度的第一孔填充层，使得在化学机械抛光（CMP）上平坦化第一孔填充层以形成一系列图案化的平面化的第一孔径填充层在一系列孔径内的狭窄台面的侵蚀被衰减。最后，然后是化学机械抛光（CMP）平坦化第一孔填充层，以在一系列孔内形成一系列图案化的平坦化的第一孔填充层。

6. 发明授权

US07611963B1 Method for forming a multi-layer shallow trench isolation structure in a semiconductor device 有权
标题翻译：在半导体器件中形成多层浅沟槽隔离结构的方法
公开(公告)号：US07611963B1
公开(公告)日：2009-11-03
申请号：US12111355
申请日：2008-04-29
申请人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
发明人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
IPC分类号： H01L21/301
CPC分类号： H01L21/76224
摘要： A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a floor and walls of the shallow trench. The method further includes forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition and forming a second doped oxide layer above the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition.
摘要翻译：描述了在半导体器件中形成多层浅沟槽隔离结构的方法。在一个实施例中，该方法包括蚀刻半导体器件的硅衬底中的浅沟槽，并在浅沟槽的地板和壁上形成介电衬垫层。该方法还包括在浅沟槽中形成第一掺杂氧化物层，第一层通过在第一处理条件下气相沉积包括硅源，氧源和掺杂源的前体形成，并形成第二掺杂氧化物层，其通过使用硅和掺杂材料的前体的气相沉积，在与第一处理条件不同的第二处理条件下进行。

7. 发明申请

US20060211250A1 Scratch reduction for chemical mechanical polishing 有权
标题翻译：化学机械抛光刮刮
公开(公告)号：US20060211250A1
公开(公告)日：2006-09-21
申请号：US11082517
申请日：2005-03-17
申请人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
发明人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31053
摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
摘要翻译：提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

8. 发明授权

US06461966B1 Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement 有权
标题翻译：高密度等离子体磷硅酸盐玻璃工艺对金属前介电应用的方法，用于等离子体损伤降低和生产率提高
公开(公告)号：US06461966B1
公开(公告)日：2002-10-08
申请号：US10017954
申请日：2001-12-14
申请人： Yao-Hsiang Chen , Chu-Yun Fu , Syung-Ming Jang
发明人： Yao-Hsiang Chen , Chu-Yun Fu , Syung-Ming Jang
IPC分类号： H01L21311
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02164 , H01L21/31625
摘要： A method of forming a composite dielectric layer comprising the following steps. A structure having at least two semiconductor structures separated by a gap therebetween is provided. A first dielectric layer is formed over the structure, the two semiconductor structures and within the gap between the two semiconductor structures to a thickness as least as high as the top of the semiconductor structures by a first high density plasma (HDP) process. The first HDP process having a first high bias RF power, a low first deposition: sputter ratio and a first chucking bias voltage. A second dielectric layer is then formed over the first dielectric layer by a second HDP process to form the composite dielectric layer. The second HDP process having: a second bias RF power that is less than the first bias RF power; a second deposition: sputter ratio that is greater than the first deposition: sputter ratio; and a second chucking bias voltage that is zero.
摘要翻译：一种形成复合电介质层的方法，包括以下步骤。提供了具有由它们之间的间隙隔开的至少两个半导体结构的结构。第一介电层通过第一高密度等离子体（HDP）工艺形成在半导体结构的两个半导体结构之间，并且在两个半导体结构之间的间隙内至少与半导体结构的顶部一样高的厚度。第一HDP工艺具有第一高偏压RF功率，低的第一沉积：溅射比和第一夹持偏置电压。然后通过第二HDP工艺在第一介电层上形成第二介电层以形成复合介电层。第二HDP处理具有：小于第一偏置RF功率的第二偏置RF功率; 第二沉积：溅射比大于第一沉积：溅射比; 和第二夹持偏置电压为零。

9. 发明授权

US06426272B1 Method to reduce STI HDP-CVD USG deposition induced defects 有权
标题翻译：降低STI HDP-CVD的方法USG沉积诱发缺陷
公开(公告)号：US06426272B1
公开(公告)日：2002-07-30
申请号：US09960808
申请日：2001-09-24
申请人： Chu-Yun Fu , Li-Jen Chen
发明人： Chu-Yun Fu , Li-Jen Chen
IPC分类号： H01L2176
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A method for shallow trench isolation formation having a thick un-biased HDP USG liner layer to reduce HDP-CVD induced defects is described. Trenches are etched through an etch stop layer into a semiconductor substrate. The semiconductor substrate is thermally oxidized to form a thermal liner layer within the isolation trenches. The isolation trenches are filled using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein the HDP-CVD process comprises: first depositing a first liner layer overlying the thermal liner layer wherein no bias power is supplied during the first depositing step and wherein the first liner layer has a thickness of between 200 and 400 Angstroms, second depositing a second liner layer using low bias power, and third depositing a gap filling layer overlying the second liner layer to fill the isolation trenches. The gap filling layer is polished back overlying the etch stop layer. The etch stop layer is removed to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
摘要翻译：描述了一种具有厚的未偏压HDP USG衬垫层以减少HDP-CVD诱导的缺陷的浅沟槽隔离形成方法。通过蚀刻停止层将沟槽蚀刻成半导体衬底。半导体衬底被热氧化以在隔离沟槽内形成热衬垫层。使用具有沉积部件和溅射部件的高密度等离子体化学气相沉积工艺（HDP-CVD）填充隔离沟槽，其中HDP-CVD工艺包括：首先沉积覆盖热衬层的第一衬垫层，其中无偏压功率在第一沉积步骤期间供应，并且其中第一衬里层具有200至400埃的厚度，使用低偏压功率沉积第二衬垫层，以及第三沉积覆盖第二衬里层的间隙填充层以填充隔离层沟渠间隙填充层被抛光回覆盖在蚀刻停止层上。去除蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区域。

10. 发明授权

US06261957B1 Self-planarized gap-filling by HDPCVD for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的HDPCVD的自平面间隙填充
公开(公告)号：US06261957B1
公开(公告)日：2001-07-17
申请号：US09378496
申请日：1999-08-20
申请人： Syun-Ming Jang , Chu-Yun Fu
发明人： Syun-Ming Jang , Chu-Yun Fu
IPC分类号： H01L2100
CPC分类号： H01L21/76229
摘要： Within a method for forming an aperture fill layer within an aperture there is first provided a topographic substrate which has formed therein a pair of mesas which defines an aperture. There is then formed over the topographic substrate and into the aperture a blanket aperture fill layer while employing a high density plasma chemical vapor deposition (HDP-CVD) method, where the blanket aperture fill layer is formed to a thickness greater than a depth of the aperture while forming a pair of protrusions over the pair of mesas. There is then etched, while employing a sputter etch method, the blanket aperture fill layer to form an etched blanket aperture fill layer such that the pair of protrusions of the blanket aperture fill layer formed over the pair of mesas is etched more rapidly than a portion of the blanket aperture fill layer formed within the aperture. Finally, there is then chemical mechanical polish (CMP) planarized the etched blanket aperture fill layer to form a patterned planarized aperture fill layer within the aperture while removing the pair of protrusions form over the pair of mesas. The method may be employed to form with enhanced planarity and attenuated residue formation a trench isolation region within an isolation trench within a semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication.
摘要翻译：在用于在孔内形成孔填充层的方法中，首先提供了形成有一对限定孔径的台面的地形衬底。然后，在使用高密度等离子体化学气相沉积（HDP-CVD）方法的同时，在地形衬底上形成覆盖孔隙填充层，并在孔中形成覆盖孔填充层，其中覆盖孔填充层形成厚度大于同时在所述一对台面上形成一对突起。然后，在采用溅射蚀刻方法的同时，将橡皮布孔填充层蚀刻，以形成蚀刻的橡皮布孔隙填充层，使得形成在该对台面上方的橡皮布孔填充层的一对突起比一部分形成在孔内的橡皮布孔填充层。最后，化学机械抛光（CMP）将蚀刻的橡皮布孔填充层平坦化，以在孔内形成图案化的平坦化孔填充层，同时从一对台面上移除一对突起。该方法可用于在半导体集成电路微电子制造中使用的半导体衬底内的隔离沟槽内的沟槽隔离区域内以增强的平面性和衰减的残留物形成形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式