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1. 发明授权

US5593919A Process for forming a semiconductor device including conductive members 失效
标题翻译：用于形成包括导电构件的半导体器件的工艺
公开(公告)号：US5593919A
公开(公告)日：1997-01-14
申请号：US523174
申请日：1995-09-05
申请人： Chii-Chang Lee , Hisao Kawasaki
发明人： Chii-Chang Lee , Hisao Kawasaki
IPC分类号： H01L21/768 , H01L21/3213
CPC分类号： H01L21/76885
摘要： The embodiments of the present invention allow the formation of interconnect and vias without forming via veils or excessive thinning of vias. Conductive members (52, 54, 56, 58) are formed with a pattern generally corresponding to the shape of interconnects. A lower intermetallic insulating layer (70)is deposited over the substrate (30) and removed over conductive members (52, 54, 56, 58) before forming via portions. Via portions are formed from the conductive members (52, 54, 56, 58). An upper intermetallic insulating layer (134) is formed and planarized to fill locations overlying the interconnect portions of the conductive members (52, 54, 56, 58) near the vias.
摘要翻译：本发明的实施例允许形成互连和通孔而不形成通过面纱或过度的通孔变薄。导电构件（52,54,56,58）形成有大致对应于互连形状的图案。在形成通孔部分之前，在衬底（30）上沉积下部金属间绝缘层（70）并且在导电构件（52,54,56,58）上移除。通孔部分由导电部件（52,54,56,58）形成。上部金属间绝缘层（134）被形成并且被平坦化以填充覆盖通孔附近的导电构件（52,54,56,58）的互连部分的位置。

2. 发明授权

US5393703A Process for forming a conductive layer for semiconductor devices 失效
标题翻译：用于形成用于半导体器件的导电层的工艺
公开(公告)号：US5393703A
公开(公告)日：1995-02-28
申请号：US150900
申请日：1993-11-12
申请人： Johnson O. Olowolafe , Hisao Kawasaki , Chii-Chang Lee
发明人： Johnson O. Olowolafe , Hisao Kawasaki , Chii-Chang Lee
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76838 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , Y10S438/927
摘要： An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.
摘要翻译：公开了用作半导体器件内的互连的铝 - 镍 - 铬（Al-Ni-Cr）层。 Al-Ni-Cr层具有约0.1-0.5重量％的镍和约0.02-0.1重量％的铬。通常，镍或铬的浓度不大于0.5重量％。该层耐电迁移和腐蚀。低镍和铬的浓度使得该层与大多数铝基层相似地沉积和图案化。

3. 发明授权

US5623166A Al-Ni-Cr conductive layer for semiconductor devices 失效
标题翻译：用于半导体器件的Al-Ni-Cr导电层
公开(公告)号：US5623166A
公开(公告)日：1997-04-22
申请号：US349219
申请日：1994-12-05
申请人： Johnson O. Olowolafe , Hisao Kawasaki , Chii-Chang Lee
发明人： Johnson O. Olowolafe , Hisao Kawasaki , Chii-Chang Lee
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76838 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , Y10S438/927
摘要： An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.
摘要翻译：公开了用作半导体器件内的互连的铝 - 镍 - 铬（Al-Ni-Cr）层。 Al-Ni-Cr层具有约0.1-0.5重量％的镍和约0.02-0.1重量％的铬。通常，镍或铬的浓度不大于0.5重量％。该层耐电迁移和腐蚀。低镍和铬的浓度使得该层与大多数铝基层相似地沉积和图案化。

4. 发明授权

US5506450A Semiconductor device with improved electromigration resistance and method for making the same 失效
标题翻译：具有改进的电迁移电阻的半导体器件及其制造方法
公开(公告)号：US5506450A
公开(公告)日：1996-04-09
申请号：US435107
申请日：1995-05-04
申请人： Chii-Chang Lee , Hisao Kawasaki
发明人： Chii-Chang Lee , Hisao Kawasaki
IPC分类号： H01L23/522 , H01L23/528 , H01L23/48 , H01L21/20
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002 , Y10S438/927
摘要： Semiconductor devices having improved electromigration resistance in their connections through dielectric layers are described. Where a conductive metal line overlies a dielectric layer and makes contact to a lower conductive structure through the dielectric layer by virtue of a conductive member, such as a tungsten plug or metal contact, the conductive metal line is provided with an end portion not otherwise connected to a conductive structure. The end portion serves as a reservoir of extra conductive material supplying the conductive metal line as the line is depleted through stress migration and/or electromigration.
摘要翻译：描述了通过介电层在其连接中具有改善的电迁移阻力的半导体器件。当导电金属线覆盖电介质层并且通过导电构件（例如钨插塞或金属接触）通过电介质层与下导电结构接触时，导电金属线设置有不另外连接的端部到导电结构。当线路通过应力迁移和/或电迁移耗尽时，端部用作提供导电金属线的额外导电材料的储存器。

5. 发明申请

US20100301487A1 IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY 有权
标题翻译：改善或相关于集成电路的可靠性
公开(公告)号：US20100301487A1
公开(公告)日：2010-12-02
申请号：US12599152
申请日：2007-05-15
申请人： Hisao Kawasaki , David Ney
发明人： Hisao Kawasaki , David Ney
IPC分类号： H01L23/48 , H01L21/768 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , H01L27/0203 , Y02P90/265
摘要： A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intrinsic parameter at the first defined value.
摘要翻译：一种制造具有最小化电迁移效应的集成电路的方法，其中所述集成电路包括一个或多个互连，所述所述或每个互连包括具有第一限定值的固有参数的介电层，其特征在于，所述方法包括：识别一个或更多的特征; 确定用于施加一个或多个第一金属元件的所述互连或每个互连的最小工艺距离; 计算可以校正所述第一定义值的内在参数的所需校正参数; 计算具有第二定义值的固有参数的第一金属元件的所需数量，使得第二定义值为第一定义值提供所需的校正参数; 以所述最小处理距离在所述互连件周围施加多个所述第一金属元件，以克服由所述固有参数在所述第一限定值处引起的电迁移的问题。

6. 发明授权

US5420072A Method for forming a conductive interconnect in an integrated circuit 失效
标题翻译：在集成电路中形成导电互连的方法
公开(公告)号：US5420072A
公开(公告)日：1995-05-30
申请号：US191896
申请日：1994-02-04
申请人： Robert W. Fiordalice , Johnson O. Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Johnson O. Olowolafe , Hisao Kawasaki
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76876 , H01L21/76843 , H01L2221/1089
摘要： A conformal titanium nitride film having a preferred crystal orientation is formed by chemically vapor depositing the film in two separate steps. In the first deposition step a titanium nitride layer (22) having poor step coverage and a preferred crystal orientation is formed. In the second deposition step a second conformal layer of titanium nitride (24) is insitu deposited onto the first titanium nitride layer (22), wherein during the deposition the first titanium nitride layer (22) acts as a crystallographic seed layer for the second titanium nitride layer (24). As a result, a titanium nitride layer exhibiting a preferred crystal orientation and good step coverage is achieved.
摘要翻译：通过在两个单独的步骤中化学气相沉积薄膜来形成具有优选<111>晶体取向的共形氮化钛薄膜。在第一沉积步骤中，形成具有差的阶梯覆盖度和优选<111>晶体取向的氮化钛层（22）。在第二沉积步骤中，氮化钛（24）的第二共形层被沉积在第一氮化钛层（22）上，其中在沉积期间，第一氮化钛层（22）用作第二钛的晶体种子层氮化物层（24）。结果，实现了具有优选<111>晶体取向和良好阶梯覆盖的氮化钛层。

7. 发明授权

US5240558A Method for forming a semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US5240558A
公开(公告)日：1993-08-31
申请号：US967294
申请日：1992-10-27
申请人： Hisao Kawasaki , Umesh Sharma , Howard C. Kirsch
发明人： Hisao Kawasaki , Umesh Sharma , Howard C. Kirsch
IPC分类号： H01L21/02 , H01L21/033 , H01L21/311 , H01L21/8242
CPC分类号： H01L27/1085 , H01L21/0331 , H01L21/0337 , H01L21/31144 , H01L28/92 , Y10S438/947
摘要： The surface area of a polysilicon electrode is increased by sputtering non-coalescing islands (20) of aluminum onto a silicon dioxide layer (18), which is overlying the polysilicon electrode. The sputtering process allows uniform island formation to be achieved independent of the deposition surface. The non-coalescing islands are then used as a mask, and a portion of the buffer layer (22) and a portion of the polysilicon electrode (26) are etched to form pillar-like regions (30) within the polysilicon electrode.
摘要翻译：通过将铝的非聚结岛（20）溅射到覆盖多晶硅电极的二氧化硅层（18）上来增加多晶硅电极的表面积。溅射工艺允许独立于沉积表面实现均匀的岛形成。然后将非聚结岛用作掩模，并且缓冲层（22）的一部分和多晶硅电极（26）的一部分被蚀刻以在多晶硅电极内形成柱状区域（30）。

8. 发明授权

US08202798B2 Improvements for reducing electromigration effect in an integrated circuit 有权
标题翻译：降低集成电路中电迁移效应的改进
公开(公告)号：US08202798B2
公开(公告)日：2012-06-19
申请号：US12675242
申请日：2007-09-20
申请人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
发明人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/7682 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterized in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
摘要翻译：一种包括一个或多个电介质层的集成电路，其中或每个电介质层设置有一个或多个互连，其中互连包括当电流流动时从互连的第一区域移动到互连的第二区域的金属原子，其特征在于互连件包括在互连的第一区域中的供体区域，用于提供金属原子，以便补偿来自第一区域的原子的移动以及用于接收金属原子的互连的第二区域处的受体区域，以便补偿运动的原子到第二个区域。

9. 发明申请

US20110221036A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110221036A1
公开(公告)日：2011-09-15
申请号：US13115251
申请日：2011-05-25
申请人： Hisao Kawasaki
发明人： Hisao Kawasaki
IPC分类号： H01L27/06 , H01L21/822
CPC分类号： H01L27/0605 , H01L21/8252 , H01L27/0629 , H01L28/60
摘要： A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
摘要翻译：提供一种具有有源元件和MIM电容器以及能够减少其制造步骤数量的结构的半导体器件及其制造方法。半导体器件具有在半导体衬底上形成具有欧姆电极的有源元件和布置在下电极和上电极之间的电介质层的MIM电容器，其中下电极和欧姆电极具有相同的结构。在其中作为有源元件的FET和MIM电容器形成在GaAs衬底10上的例如作为FET的欧姆电极的源电极16a和漏电极16b的MMIC100中，与 MIM电容器的下电极16c。这里，电极由相同的金属形成。

10. 发明授权

US07829919B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07829919B2
公开(公告)日：2010-11-09
申请号：US12368557
申请日：2009-02-10
申请人： Hisao Kawasaki
发明人： Hisao Kawasaki
IPC分类号： H01L29/812
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： A semiconductor device which can prevent peeling off of a gate electrode is provided. The semiconductor device has GaN buffer layer 12 formed on substrate 11, undoped AlGaN layer 13 formed on this buffer layer 12, drain electrode 16 and source electrode 17 formed separately on undoped AlGaN layer 13, which form ohmic junctions with undoped AlGaN layer 13. Between drain electrode 16 and source electrode 17, insulating layer 20 which has opening 19 is formed, and metal film 21 is formed on a surface of insulating layer 2. Gate electrode 18 which forms a Schottky barrier junction with undoped AlGaN layer 13 is formed in opening 19, and gate electrode 18 adheres to metal film 21.
摘要翻译：提供了能够防止栅电极剥离的半导体装置。半导体器件具有形成在衬底11上的GaN缓冲层12，形成在该缓冲层12上的未掺杂的AlGaN层13，漏电极16和与未掺杂的AlGaN层13形成欧姆结的未掺杂的AlGaN层13上的源电极17。漏电极16和源电极17，形成有开口19的绝缘层20，并且在绝缘层2的表面上形成金属膜21.形成与未掺杂的AlGaN层13形成肖特基势垒结的栅电极18形成为开口 19，栅电极18附着于金属膜21。

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