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1. 发明授权

US07847611B2 Level shifter with reduced power consumption and low propagation delay 有权
标题翻译：电平移位器具有降低的功耗和低传播延迟
公开(公告)号：US07847611B2
公开(公告)日：2010-12-07
申请号：US12357179
申请日：2009-01-21
申请人： Chih-Wen Yang , Sheng-Hua Chen
发明人： Chih-Wen Yang , Sheng-Hua Chen
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.
摘要翻译：电平移位器包括耦合到信号输入并可在第一高电平和低电平之间操作的“否”门; 耦合到第二电压源和控制端的第一PMOS晶体管; 耦合到第一PMOS晶体管的第一NMOS晶体管，非栅极输出端和参考电压; 以及耦合到信号输入，非栅极输出端和第二电压源的控制电路。当信号输入和非栅极输出端分别处于第一高电平和低电平时，第一PMOS晶体管导通，使得信号输出处于第二高电平; 并且当信号输入和非栅极输出端相反地切换时，第一PMOS晶体管被截止并且信号输出处于低电平。

2. 发明授权

US08824172B2 Apparatus and method for standby power reduction of a flyback power converter 有权
标题翻译：反激式功率转换器的待机功率降低的装置和方法
公开(公告)号：US08824172B2
公开(公告)日：2014-09-02
申请号：US12852628
申请日：2010-08-09
申请人： Sheng-Hua Chen , Tzu-Chen Lin , Pei-Lun Huang
发明人： Sheng-Hua Chen , Tzu-Chen Lin , Pei-Lun Huang
IPC分类号： H02M3/335 , H02M1/00
CPC分类号： H02M3/33507 , H02M2001/0032 , Y02B70/16
摘要： An apparatus and method for a flyback power converter reduce the standby output voltage of the flyback power converter by switching the reference voltage provided by a shunt regulator of the flyback power converter or the ratio of voltage divider resistors of the shunt regulator, to reduce the standby power consumption by an output feedback circuit of the flyback power converter, the shunt regulator, and the voltage divider resistors, and thereby improve the power loss of the flyback power converter in standby mode.
摘要翻译：用于回扫功率转换器的装置和方法通过切换由回扫功率转换器的并联调节器提供的参考电压或分流调节器的分压电阻器的比例来减小反激式功率转换器的备用输出电压，以减少待机反激式功率转换器的输出反馈电路，分流调节器和分压电阻器的功耗，从而提高回扫功率转换器在待机模式下的功率损耗。

3. 发明授权

US09250295B2 High-voltage battery charging simulation system and operating method thereof 有权
标题翻译：高压电池充电模拟系统及其运行方法
公开(公告)号：US09250295B2
公开(公告)日：2016-02-02
申请号：US13553811
申请日：2012-07-19
申请人： Shean-Kwang Chou , Hung-Hsi Lin , Chih-Hung Lin , Sheng-Hua Chen
发明人： Shean-Kwang Chou , Hung-Hsi Lin , Chih-Hung Lin , Sheng-Hua Chen
IPC分类号： G06G7/54 , G01R31/36
CPC分类号： G01R31/36 , G01R31/3651
摘要： The present invention relates to a high-voltage battery charging simulation system that includes a simulation high-voltage battery pack, a simulation battery management system, a multi-party communication device, and a charging station. The voltage of the simulation high-voltage battery pack can be calculated and updated immediately by the simulation battery management system to simulate the feature of real battery pack, so that it can detect the operation of the multi-party communication device and the charging station.
摘要翻译：本发明涉及一种高压电池充电模拟系统，其包括模拟高电压电池组，模拟电池管理系统，多方通信装置和充电站。仿真高压电池组的电压可以通过模拟电池管理系统立即计算和更新，以模拟实际电池组的特征，从而可以检测多方通信设备和充电站的运行情况。

4. 发明申请

US20050128670A1 Input/output buffer protection circuit 有权
标题翻译：输入/输出缓冲保护电路
公开(公告)号：US20050128670A1
公开(公告)日：2005-06-16
申请号：US10735324
申请日：2003-12-12
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H01L27/02 , H03K19/003 , H02H3/20
CPC分类号： H03K19/00315 , H01L27/0266
摘要： An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.
摘要翻译：输入/输出缓冲器保护电路，其包括I / O焊盘，I / O缓冲器，n阱控制电路，栅极控制电路和保护部件。 I / O缓冲器包括PMOS晶体管和NMOS晶体管。 n阱控制电路耦合到PMOS晶体管的n阱。当施加高于源电压的输入电压时，PMOS的n阱处的电压由n阱控制电路增加到输入电压电平。栅极控制电路耦合到PMOS晶体管的栅极端子和输入/输出焊盘。当施加高于源极电压的输入电压时，PMOS栅极端子处的电压由栅极控制电路增加到源极电压电平。其中栅极控制电路包括晶体管，并且晶体管在输出模式下将高电位控制电压传送到PMOS晶体管的栅极。保护元件耦合在晶体管的栅极和I / O焊盘之间，以产生电压降降路径，并阻止I / O焊盘信号流回晶体管的栅极。

5. 发明申请

US20050068069A1 INPUT/OUTPUT BUFFER 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US20050068069A1
公开(公告)日：2005-03-31
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

6. 发明申请

US20080178135A1 CELLS OF INTEGRATED CIRCUIT AND RELATED TECHNOLOGY AND METHOD 审中-公开
标题翻译：集成电路及相关技术与方法
公开(公告)号：US20080178135A1
公开(公告)日：2008-07-24
申请号：US11829870
申请日：2007-07-27
申请人： Jeng-Huang Wu , Sheng-Hua Chen , Meng-Jer Wey
发明人： Jeng-Huang Wu , Sheng-Hua Chen , Meng-Jer Wey
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights equal to a non-integer multiplication of the routing track to establish a cell library, so a layout area of each cell is reduced. Further, higher integration of integrated circuit can be achieved by applying the proposed cells in integrated circuits.
摘要翻译：能够实现集成电路高集成度的电子电池/电池库及相关技术/方法。在一个实施例中，所提出的技术采用具有等于路由轨道的非整数乘法的单元高度的单元，以建立单元库，从而减小每个单元的布局面积。此外，通过在集成电路中应用所提出的单元，可以实现集成电路的更高集成度。

7. 发明授权

US07057468B2 Crystal oscillator circuit with activation control 失效
标题翻译：晶振电路具有启动控制功能
公开(公告)号：US07057468B2
公开(公告)日：2006-06-06
申请号：US10876083
申请日：2004-06-24
申请人： Jeng-Huang Wu , Sheng-Hua Chen
发明人： Jeng-Huang Wu , Sheng-Hua Chen
IPC分类号： H03B1/00 , H03L5/00 , G06F1/04
CPC分类号： H03K3/0307
摘要： A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.
摘要翻译： CMOS皮尔斯晶体振荡器。具有启动控制的时钟发生器，用于产生时钟信号。时钟发生器包括放大器，整形电路和诊断电路。放大器能够通过输入焊盘和输出焊盘耦合到外部振荡源以产生振荡信号，整形电路能够耦合到输出焊盘，用于整形振荡信号以产生时钟信号，并且诊断电路能够耦合到输出焊盘，用于当振荡信号的振幅超过全摆幅电压的预定部分时断言就绪信号。

8. 发明授权

US06882188B1 Input/output buffer 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US06882188B1
公开(公告)日：2005-04-19
申请号：US10673391
申请日：2003-09-30
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03B1/00
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.
摘要翻译：一个输入/输出缓冲区。输入/输出电路具有耦合到I / O焊盘和浮动N阱区的传输端。 P栅极控制电路将第二栅极控制信号传送到第一PMOS晶体管的栅极。反馈检测装置耦合在传输终端和N阱控制电路之间，以根据I / O焊盘的输入电压输出反馈信号。 N阱控制电路根据从反馈检测装置输出的反馈信号，调整第一PMOS晶体管的N阱区域的电压电平。

9. 发明授权

US06861874B1 Input/output buffer 有权
标题翻译：输入/输出缓冲器
公开(公告)号：US06861874B1
公开(公告)日：2005-03-01
申请号：US10679399
申请日：2003-10-07
申请人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
发明人： Sheng-Hua Chen , Hung-Yi Chang , Jeng-Huang Wu
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.
摘要翻译：一个输入/输出缓冲区。输入/输出电路由第一PMOS晶体管和第一NMOS晶体管组成，具有耦合到I / O焊盘的I / O端口和N阱区域。 N阱控制电路根据I / O焊盘上的输入信号来控制第一PMOS晶体管的N阱区域的电压电平。 P栅极控制电路接收第二栅极控制信号并输出到第一PMOS晶体管的栅极。 P栅极控制电路由传输栅极和第三PMOS晶体管构成。传输栅极和第三PMOS晶体管不必遵循ESD的设计规则，因为P栅极控制电路不直接连接到I / O，所以P栅极控制电路所需的晶片面积可以减小垫。

10. 发明申请

US20130271065A1 HIGH-VOLTAGE BATTERY CHARGING SIMULATION SYSTEM AND OPERATING METHOD THEREOF 有权
标题翻译：高压电池充电仿真系统及其工作方法
公开(公告)号：US20130271065A1
公开(公告)日：2013-10-17
申请号：US13553811
申请日：2012-07-19
申请人： SHEAN-KWANG CHOU , Hung-Hsi Lin , Chih-Hung Lin , Sheng-Hua Chen
发明人： SHEAN-KWANG CHOU , Hung-Hsi Lin , Chih-Hung Lin , Sheng-Hua Chen
IPC分类号： H02J7/00
CPC分类号： G01R31/36 , G01R31/3651
摘要： The present invention relates to a high-voltage battery charging simulation system that includes a simulation high-voltage battery pack, a simulation battery management system, a multi-party communication device, and a charging station. The voltage of the simulation high-voltage battery pack can be calculated and updated immediately by the simulation battery management system to simulate the feature of real battery pack, so that it can detect the operation of the multi-party communication device and the charging station.
摘要翻译：本发明涉及一种高压电池充电模拟系统，其包括模拟高电压电池组，模拟电池管理系统，多方通信装置和充电站。仿真高压电池组的电压可以通过模拟电池管理系统立即计算和更新，以模拟实际电池组的特征，从而可以检测多方通信设备和充电站的运行情况。

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