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    • 5. 发明申请
    • Low noise high isolation transmit buffer gain control mechanism
    • 低噪声高隔离传输缓冲器增益控制机制
    • US20050287967A1
    • 2005-12-29
    • US11115815
    • 2005-04-26
    • Chih-Ming HungFrancis CruiseDirk LeipoldRobert Staszewski
    • Chih-Ming HungFrancis CruiseDirk LeipoldRobert Staszewski
    • H01Q11/12H03F1/32H03F3/191H04B1/04
    • H04B1/0483H03F1/3241H03F1/3294H03F3/191H03F2200/331
    • A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
    • 一种低噪声,高隔离,全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器(DRAC)的上下文中呈现,该转换器有效地结合了上变频,I和Q组合,D / A转换,滤波,缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门,其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时,通过识别伪E类预功率放大器(PPA)所遭受的损伤来实现功率控制。 首先,阵列的NMOS开关具有大的导通电阻,因此当输入波形为高时,只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制,并允许控制RF输出功率的全数字方法。
    • 8. 发明授权
    • Harmonic suppression device
    • 谐波抑制装置
    • US08217735B2
    • 2012-07-10
    • US12603654
    • 2009-10-22
    • Shyue-Dar ChenChih-Ming Hung
    • Shyue-Dar ChenChih-Ming Hung
    • H03H7/00H03F3/213H04B1/04
    • H01P1/20345H03F1/32H03F3/60
    • A harmonic suppression device includes a multilayer printed circuit board (PCB). The multilayer PCB includes a first layer, a second layer, and a third layer. The third layer is connected to the ground. The first layer is configured with a power amplifier, an input microstrip, a voltage divider microstrip, and an output microstrip. The power amplifier is operable to amplify radio frequency (RF) signals input using the input microstrip and to output the amplified RF signals using the output microstrip. The second layer is configured with a first microstrip and a second microstrip. One end of each of the first and second microstrips is connected to an alternative one of the first layer and the third layer by vias, and the other ends of the first and second microstrips are unattached so as to suppress harmonics on the power amplifier.
    • 谐波抑制装置包括多层印刷电路板(PCB)。 多层PCB包括第一层,第二层和第三层。 第三层连接到地面。 第一层配置有功率放大器,输入微带线,分压器微带线和输出微带线。 功率放大器可用于放大使用输入微带输入的射频(RF)信号,并使用输出微带输出放大的RF信号。 第二层配置有第一微带和第二微带。 第一和第二微带中的每一个的一端通过通孔连接到第一层和第三层中的另一个,并且第一和第二微带的另一端未连接,以便抑制功率放大器上的谐波。