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1. 发明授权

US08405135B2 3D via capacitor with a floating conductive plate for improved reliability 有权
标题翻译： 3D通过具有浮动导电板的电容器，以提高可靠性
公开(公告)号：US08405135B2
公开(公告)日：2013-03-26
申请号：US12898340
申请日：2010-10-05
申请人： Chih-Chao Yang , Fen Chen , Baozhen Li
发明人： Chih-Chao Yang , Fen Chen , Baozhen Li
IPC分类号： H01L27/108
CPC分类号： H01L23/5223 , H01L21/76805 , H01L25/0657 , H01L28/91 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
摘要翻译：本发明提供一种3D通孔电容器及其形成方法。电容器包括在基板上的绝缘层。绝缘层具有通孔，其具有侧壁和底部。第一电极覆盖通孔的侧壁和底部的至少一部分。第一高k电介质材料层覆盖在第一电极上。第一导电板在第一高k电介质材料层之上。第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。在通孔的剩余部分中形成第二电极。第一导电板基本上平行于第一电极并且不与第一和第二电极接触。还提供了这种3D通孔电容器的阵列。

2. 发明申请

US20120080771A1 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY 有权
标题翻译：具有改进可靠性的浮动导电板的3D VIA电容器
公开(公告)号：US20120080771A1
公开(公告)日：2012-04-05
申请号：US12898340
申请日：2010-10-05
申请人： Chih-Chao Yang , Fen Chen , Baozhen Li
发明人： Chih-Chao Yang , Fen Chen , Baozhen Li
IPC分类号： H01L27/08 , H01L21/02
CPC分类号： H01L23/5223 , H01L21/76805 , H01L25/0657 , H01L28/91 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
摘要翻译：本发明提供一种3D通孔电容器及其形成方法。电容器包括在基板上的绝缘层。绝缘层具有通孔，其具有侧壁和底部。第一电极覆盖通孔的侧壁和底部的至少一部分。第一高k电介质材料层覆盖在第一电极上。第一导电板在第一高k电介质材料层之上。第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。在通孔的剩余部分中形成第二电极。第一导电板基本上平行于第一电极并且不与第一和第二电极接触。还提供了这种3D通孔电容器的阵列。

3. 发明授权

US08642460B2 Semiconductor switching device and method of making the same 失效
标题翻译：半导体开关器件及其制造方法
公开(公告)号：US08642460B2
公开(公告)日：2014-02-04
申请号：US13155757
申请日：2011-06-08
申请人： Chih-Chao Yang , Stephen A Cohen , Baozhen Li
发明人： Chih-Chao Yang , Stephen A Cohen , Baozhen Li
IPC分类号： H01L21/44
CPC分类号： B82Y10/00 , H01L23/5252 , H01L29/413 , H01L2924/0002 , H01L2924/00
摘要： A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided.
摘要翻译：一种开关装置，包括具有第一顶表面的第一介电层，嵌入在第一介电层中的两个导电特征，每个导电特征具有与第一介电层的第一顶表面基本上共面的第二顶表面，以及一组在两个导电特征之间的低扩散迁移率金属的离散岛。低扩散迁移率金属的离散岛可以在第一顶表面上或嵌入在第一介电层中。当规定的电压施加到两个导电特征时，开关装置的两个导电特征的电导率增加。还提供了一种形成这种开关装置的方法。

4. 发明授权

US08421186B2 Electrically programmable metal fuse 有权
标题翻译：电子可编程金属保险丝
公开(公告)号：US08421186B2
公开(公告)日：2013-04-16
申请号：US13149108
申请日：2011-05-31
申请人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
发明人： Baozhen Li , Chunyan E. Tian , Chih-Chao Yang
IPC分类号： H01L29/00 , H01L23/525 , H01H37/76
CPC分类号： H01L23/5256 , G11C17/16 , G11C29/785 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.
摘要翻译：金属电可编程保险丝（eFuse）包括在金属条的两端处具有与宽金属线部分相邻的金属线的具有宽度大于金属带宽度的宽度的金属带。条带宽度可以是光刻最小尺寸，并且金属条带的长度与条带宽度的比率大于5以在编程期间定位围绕金属条的中心的加热。加热的本地化减少了用于编程金属eFuse所需的电力。此外，在金属带的长于Blech长度的部分内的编程期间形成逐渐的温度梯度，使得金属的电迁移在金属带的中心部分逐渐发生。金属线部分提供与金属eFuse相同的水平，以物理阻挡编程期间产生的碎屑。

5. 发明申请

US20140048927A1 METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：在集成电路设备中提高精细线路可靠性的方法
公开(公告)号：US20140048927A1
公开(公告)日：2014-02-20
申请号：US13587998
申请日：2012-08-17
申请人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/76838 , H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.
摘要翻译：用于形成半导体结构的结构和方法。半导体结构包括包括至少一个铜互连层的多个层。铜互连层在半导体结构中的物理相邻层之一和半导体结构中的集成电路和电子器件之间提供电导体。多个螺柱被定位在所述至少一个铜互连层内。螺栓间隔开小于或等于至少一个铜互连层的Blech长度的距离。漂浮长度是低于该值的长度，在该长度之下不会发生由于至少一个铜互连层内的金属原子的电迁移而导致的损伤。多个螺柱包括铜原子扩散阻挡层。

6. 发明申请

US20100314764A1 HYBRID METALLIC WIRE AND METHODS OF FABRICATING SAME 失效
标题翻译：混合金属线及其制造方法
公开(公告)号：US20100314764A1
公开(公告)日：2010-12-16
申请号：US12482777
申请日：2009-06-11
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.
摘要翻译：一种制造结构的结构和方法。该结构包括：介电层中的沟槽; 导电衬垫，导电芯导体和填充所述衬套和所述芯导体之间的空隙的导电填充材料。

7. 发明授权

US07692439B2 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

8. 发明授权

US07585764B2 VIA bottom contact and method of manufacturing same 有权
标题翻译： VIA底部接触及其制造方法相同
公开(公告)号：US07585764B2
公开(公告)日：2009-09-08
申请号：US11161599
申请日：2005-08-09
申请人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

9. 发明申请

US20070037403A1 VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME 有权
标题翻译：通过底部接触及其制造方法
公开(公告)号：US20070037403A1
公开(公告)日：2007-02-15
申请号：US11161599
申请日：2005-08-09
申请人： Kaushik Chanda , Lawrence Clevenger , Andrew Cowley , Jason Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence Clevenger , Andrew Cowley , Jason Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

10. 发明申请

US20130071998A1 Electrical Fuse With Metal Line Migration 审中-公开
标题翻译：具有金属线迁移的电气保险丝
公开(公告)号：US20130071998A1
公开(公告)日：2013-03-21
申请号：US13234205
申请日：2011-09-16
申请人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/326 , H01L21/28 , H01L23/52
CPC分类号： H01L23/5256 , H01L21/326 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.
摘要翻译：公开了一种电熔丝装置。电路装置可以包括熔丝装置，第一电路元件和第二电路元件。熔丝包括具有第一电迁移电阻的第一触点，具有第二电迁移电阻的第二触点和耦合到第一触点和第二触点的金属线，其具有低于第二次电迁移阻力。第一电路元件耦合到第一触点，而第二电路元件耦合到第二触点。保险丝被配置为通过金属线将编程电流从第一触点传导到第二触点。此外，编程电流使金属线电离远离第二触点，以将第二电路元件与第一电路元件电隔离。

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