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1. 发明授权

US5636320A Sealed chamber with heating lamps provided within transparent tubes 失效
标题翻译：带加热灯的密封室设在透明管内
公开(公告)号：US5636320A
公开(公告)日：1997-06-03
申请号：US452466
申请日：1995-05-26
申请人： Chienfan Yu , David E. Kotecki , Wesley C. Natzle
发明人： Chienfan Yu , David E. Kotecki , Wesley C. Natzle
IPC分类号： C30B25/10 , C30B31/12 , F26B3/28 , H01L21/205 , F26B19/00 , F27D1/00
CPC分类号： C30B25/10 , C30B31/12 , F26B3/283
摘要： A reactor is provided for heating a workpiece in a sealed environment. The reactor has a chamber with a gas inlet port, a gas outlet port, and at least one tube for receiving a heat source. The tube passes from outside the chamber into the inside of the chamber without breaking the chamber seal. Alternately, the tubes may be used for treating the workpiece with light, in combination with or instead of heat treatment.
摘要翻译：提供反应器用于在密封环境中加热工件。反应器具有具有气体入口，气体出口和至少一个用于接收热源的管的室。管从腔室外部进入腔室内部，而不破坏腔室密封。替代地，管可以用于与光结合或代替热处理用于处理工件。

2. 发明授权

US6054328A Method for cleaning the surface of a dielectric 失效
标题翻译：清洁电介质表面的方法
公开(公告)号：US6054328A
公开(公告)日：2000-04-25
申请号：US761166
申请日：1996-12-06
申请人： Peter R. Duncombe , David E. Kotecki , Robert B. Laibowitz , Wesley Natzle , Chienfan Yu
发明人： Peter R. Duncombe , David E. Kotecki , Robert B. Laibowitz , Wesley Natzle , Chienfan Yu
IPC分类号： H01L21/02 , H01L21/306 , H01L21/311 , H01L21/316 , H01L21/00
CPC分类号： H01L21/31122 , H01L21/31691 , H01L21/02052 , H01L21/31111 , H01L28/55
摘要： This invention relates to a method for improving the chemical and electrical performance characteristics of a high dielectric constant material. The method comprises the steps of first obtaining a barium containing high dielectric constant material, the material having an upper surface and then modifying the surface chemistry of said upper surface by interacting said upper surface with a gas reactant in a closed environment. In a variant of the method, the gas reactant preferentially reacting with upper surface as compared to the bulk.
摘要翻译：本发明涉及一种改善高介电常数材料的化学和电学性能特性的方法。该方法包括以下步骤：首先获得含钡高介电常数材料，该材料具有上表面，然后通过在封闭环境中与气体反应物相互作用来改变所述上表面的表面化学性质。在该方法的变体中，气体反应物与体积相比优先与上表面反应。

3. 发明授权

US06178082B1 High temperature, conductive thin film diffusion barrier for ceramic/metal systems 失效
标题翻译：陶瓷/金属系统的高温导电薄膜扩散屏障
公开(公告)号：US06178082B1
公开(公告)日：2001-01-23
申请号：US09031236
申请日：1998-02-26
申请人： Mukta S. Farooq , David E. Kotecki , Robert A. Rita , Stephen M. Rossnagel
发明人： Mukta S. Farooq , David E. Kotecki , Robert A. Rita , Stephen M. Rossnagel
IPC分类号： H01G4005
CPC分类号： H01L23/49894 , H01L21/28568 , H01L23/49827 , H01L23/49866 , H01L28/75 , H01L2224/16 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/15311 , H01L2924/19103 , H05K1/0306 , H05K1/162
摘要： A multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process. A method is also provided for fabricating an interposer capacitor with a multilayer ceramic substrate base and a thin film multilayer structure having at least one capacitor comprising at least one bottom platinum electrode.
摘要翻译：提供具有包含与其连接的电容器的薄膜结构的多层陶瓷基板作为插入电容器，该电容器采用铂作为电容器的底部电极。在优选的电容器中，使用诸如钛酸钡的电介质材料作为电容器电极之间的电介质材料。中间层电容器的制造需要原位或后沉积高温退火，并且使用这种电介质需要在非还原气氛中加热电容器结构。在电极和下面的多层陶瓷基板之间的下铂电极上的诸如TaSiN的高温薄膜扩散阻挡层的层防止或最小化在制造期间薄膜结构连接到的多层陶瓷基板的金属化的氧化处理。还提供了一种用于制造具有多层陶瓷衬底基底和具有至少一个包括至少一个底部铂电极的电容器的薄膜多层结构的插入式电容器的方法。

4. 发明授权

US6124199A Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
标题翻译：同时形成储存电容电极和互连的方法
公开(公告)号：US6124199A
公开(公告)日：2000-09-26
申请号：US300900
申请日：1999-04-28
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L21/02 , H01L21/8242 , H01L23/522 , H01H21/4763
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

5. 发明授权

US6010748A Method of delivering source reagent vapor mixtures for chemical vapor deposition using interiorly partitioned injector 失效
标题翻译：使用内部分隔的注射器输送用于化学气相沉积的源试剂蒸汽混合物的方法
公开(公告)号：US6010748A
公开(公告)日：2000-01-04
申请号：US17384
申请日：1998-02-03
申请人： Peter C. Van Buskirk , James A. Fair , David E. Kotecki
发明人： Peter C. Van Buskirk , James A. Fair , David E. Kotecki
IPC分类号： C23C16/44 , C23C16/455 , C23C16/40
CPC分类号： C23C16/45565 , C23C16/455
摘要： A showerhead disperser device for mixing plural vapor streams, comprising: a housing including front and rear walls in spaced apart relation to one another, and a side wall therebetween, defining within the housing an interior volume; the front wall having a multiplicity of vapor mixture discharge openings therein, for discharging mixed vapor from the interior volume of the housing exteriorly thereof, flow passages joined to the housing for introducing into the interior volume of the housing respective fluids to be mixed therein; and at least one baffle plate mounted in the interior volume of the housing, intermediate the front and rear walls of the housing, the baffle plate having an edge in spaced relation to the side wall to form an annular flow passage therebetween and the baffle plate having at least one of the respective fluids directed thereagainst upon introduction to the interior volume of the housing, for distribution thereof in the interior volume of the housing. The baffled showerhead disperser is usefully employed to enable formation of CVD thin films of highly uniform composition and thickness.
摘要翻译：一种用于混合多个蒸汽流的喷头分散装置，包括：壳体，其包括彼此间隔开的前壁和后壁以及其间的侧壁，在所述壳体内限定内部容积; 所述前壁在其中具有多个蒸汽混合物排出口，用于从其外部的所述壳体的内部容积排出混合蒸气，流动通道连接到所述壳体，以将待混合的各种流体引入到所述壳体的内部容积中; 以及安装在所述壳体的内部容积中的至少一个挡板，位于所述壳体的前壁和后壁之间，所述挡板具有与所述侧壁间隔开的边缘，以在其间形成环形流动通道，并且所述挡板具有各个流体中的至少一个在引入壳体的内部空间时被引导到其上，以将其分配在壳体的内部空间中。挡板式喷头分散机有利地用于形成高度均匀组成和厚度的CVD薄膜。

6. 发明授权

US5268069A Safe method for etching silicon dioxide 失效
标题翻译：蚀刻二氧化硅的安全方法
公开(公告)号：US5268069A
公开(公告)日：1993-12-07
申请号：US895493
申请日：1992-06-08
申请人： Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki , Andrew H. Simon , Manu Tejwani
发明人： Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki , Andrew H. Simon , Manu Tejwani
IPC分类号： H01L21/306 , H01L21/311 , H01L21/00
CPC分类号： H01L21/02046 , H01L21/02049 , H01L21/31116
摘要： Anhydrous ammonium fluoride is used as a safe source of hydrogen fluoride for etching native or other silicon dioxide layers from silicon substrates. Heating the anhydrous ammonium fluoride above its sublimation temperature results in the generation of hydrogen fluoride gas which etches the silicon dioxide. Controlled amounts of water vapor are used during the etch reaction to ensure complete etching of the thin oxide layers down to within hundredths of a monolayer and to achieve precise etch rate control.
摘要翻译：无水氟化铵用作氟化氢的安全源，用于从硅衬底蚀刻天然或其他二氧化硅层。在其升华温度以上加热无水氟化铵导致产生二氧化硅蚀刻的氟化氢气体。在蚀刻反应期间使用受控量的水蒸气，以确保将薄氧化物层完全蚀刻到百分之几以下的单层并且实现精确的蚀刻速率控制。

7. 发明授权

US5134963A LPCVD reactor for high efficiency, high uniformity deposition 失效
标题翻译： LPCVD反应器用于高效率，高均匀性沉积
公开(公告)号：US5134963A
公开(公告)日：1992-08-04
申请号：US784160
申请日：1991-10-28
申请人： Steven G. Barbee , Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki
发明人： Steven G. Barbee , Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki
IPC分类号： C23C16/52 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/205
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45504 , C30B25/14
摘要： An injector with a convex wall surface facing the susceptor directs vapor toward a wafer held by a susceptor producing a generally laminar flow across the surface of the wafer that in combination with the convex wall surface prevents formation of recirculation cells in the region between the wafer and the injector.

8. 发明授权

US06429474B1 Storage-capacitor electrode and interconnect 失效
标题翻译：储存电容电极和互连
公开(公告)号：US06429474B1
公开(公告)日：2002-08-06
申请号：US09547335
申请日：2000-04-11
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

9. 发明授权

US06395594B2 Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
标题翻译：同时形成储存电容电极和互连的方法
公开(公告)号：US06395594B2
公开(公告)日：2002-05-28
申请号：US09750790
申请日：2001-01-02
申请人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
发明人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10882 , H01L27/10894
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括用于制造两种类型互连的至少一个并且优选两个电容器电极。制造DRAM存储单元的方法包括：形成一个或多个电容电极，同时形成存储单元的存储电容器的电极，以及与辅助电容器电极相同的材料。

10. 发明授权

US06355567B1 Retrograde openings in thin films 失效
标题翻译：薄膜逆行开口
公开(公告)号：US06355567B1
公开(公告)日：2002-03-12
申请号：US09345646
申请日：1999-06-30
申请人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
发明人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
IPC分类号： H01L21311
CPC分类号： H01L21/76879 , H01L21/31116 , H01L21/76804 , H01L21/7682 , H01L21/76885
摘要： Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.
摘要翻译：薄膜中的逆行开口及其形成方法。开口可以包括形成在开口内的导电材料，以用作包括具有锥形横截面的导线的布线图案。该方法涉及用于在膜内形成具有影响所选择的蚀刻剂物质的蚀刻速率的特性梯度的逆向开口的两步蚀刻方法。首先通过各向异性蚀刻工艺在膜内形成开口。然后通过对特性有选择性的各向同性蚀刻工艺将开口转换成包括逆行特征的开口。此后，逆行开口填充有导电材料，在一种情况下，通过电镀或其它沉积技术。

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