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1. 发明申请

US20080251827A1 Checkerboard deep trench dynamic random access memory cell array layout 有权
标题翻译：棋盘深沟动态随机存取存储单元阵列布局
公开(公告)号：US20080251827A1
公开(公告)日：2008-10-16
申请号：US11776558
申请日：2007-07-12
申请人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
发明人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10885 , H01L27/10888 , Y10S257/905 , Y10S257/906
摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.
摘要翻译：公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

2. 发明授权

US07535045B2 Checkerboard deep trench dynamic random access memory cell array layout 有权
标题翻译：棋盘深沟动态随机存取存储单元阵列布局
公开(公告)号：US07535045B2
公开(公告)日：2009-05-19
申请号：US11776558
申请日：2007-07-12
申请人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
发明人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10885 , H01L27/10888 , Y10S257/905 , Y10S257/906
摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.
摘要翻译：公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

3. 发明授权

US08309998B2 Memory structure having a floating body and method for fabricating the same 有权
标题翻译：具有浮体的存储结构及其制造方法
公开(公告)号：US08309998B2
公开(公告)日：2012-11-13
申请号：US13102039
申请日：2011-05-05
申请人： Tzung-Han Lee , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/7841 , H01L27/10802 , H01L29/66666 , H01L29/7827
摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.
摘要翻译：提供一种具有浮体的存储器结构，其包括：衬底，其包括有源区域和围绕有源区域的隔离结构;有源区域中的衬底中的第一源极/漏极区域;位于衬底中的第一浮置体第一源极/漏极区域，第一浮体上的第二浮体，第二浮体上的第二源极/漏极区域，以及衬底中的沟槽型栅极结构以及第一浮体旁边。还提供了一种制造具有浮体的存储结构的方法。

4. 发明授权

US07633109B2 DRAM structure and method of making the same 有权
标题翻译： DRAM结构和制作方法
公开(公告)号：US07633109B2
公开(公告)日：2009-12-15
申请号：US11965769
申请日：2007-12-28
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/4236
摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。表面带用于将漏极区域电连接到沟槽电容器。

5. 发明申请

US20090008691A1 DRAM STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译： DRAM结构及其制作方法
公开(公告)号：US20090008691A1
公开(公告)日：2009-01-08
申请号：US11965769
申请日：2007-12-28
申请人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
发明人： Tzung-Han Lee , Chih-Hao Cheng , Te-Yin Chen , Chung-Yuan Lee , En-Jui Li
IPC分类号： H01L27/108
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/4236
摘要： A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
摘要翻译： DRAM结构具有衬底，具有翅片结构的埋入晶体管，沟槽电容器和衬底表面上的表面带。表面带用于将漏极区域电连接到沟槽电容器。

6. 发明申请

US20080318377A1 METHOD OF FORMING SELF-ALIGNED GATES AND TRANSISTORS 审中-公开
标题翻译：形成自对准栅和晶体管的方法
公开(公告)号：US20080318377A1
公开(公告)日：2008-12-25
申请号：US11964720
申请日：2007-12-27
申请人： Tzung-Han Lee , Chih-Hao Cheng , Pei-Tzu Lee , Te-Yin Chen , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Pei-Tzu Lee , Te-Yin Chen , Chung-Yuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10879 , H01L29/66787 , H01L29/7851
摘要： Method for fabricating a self-aligned gate of a transistor including: forming a plurality of deep trench capacitors in a substrate, concurrently forming a surface strap and a contact pad on a surface of the substrate, wherein a spacing between the surface strap and the contact pad exposes a portion of an active area, filling the spacing with a dielectric layer, forming a photoresist pattern on the substrate, wherein the photoresist has an opening situated directly above the spacing between the surface strap and the contact pad, etching away the dielectric layer and a portion of a shallow trench isolation region through the opening thereby forming an upwardly protruding fin-typed channel structure, forming a gate dielectric layer on the upwardly protruding fin-typed channel structure, and forming a gate on the gate dielectric layer.
摘要翻译：一种用于制造晶体管的自对准栅极的方法，包括：在衬底中形成多个深沟槽电容器，同时在衬底的表面上形成表面带和接触焊盘，其中表面带和触点之间的间隔衬垫暴露有源区的一部分，用介电层填充间隔，在衬底上形成光致抗蚀剂图案，其中光致抗蚀剂具有位于表面带和接触垫之间的间隔正上方的开口，蚀刻掉介电层以及通过开口的浅沟槽隔离区域的一部分，从而形成向上突出的鳍状沟道结构，在向上突出的鳍状沟道结构上形成栅极电介质层，并在栅极电介质层上形成栅极。

7. 发明授权

US08455319B2 Vertical transistor for random-access memory and manufacturing method thereof 有权
标题翻译：用于随机存取存储器的垂直晶体管及其制造方法
公开(公告)号：US08455319B2
公开(公告)日：2013-06-04
申请号：US13039523
申请日：2011-03-03
申请人： Tzung Han Lee , Chung-Yuan Lee , Hsien-Wen Liu
发明人： Tzung Han Lee , Chung-Yuan Lee , Hsien-Wen Liu
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/10802 , H01L29/7841
摘要： A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.
摘要翻译：一种用于随机存取存储器的垂直晶体管的制造方法，具有以下步骤：在半导体衬底上限定有源区; 在活性区域外形成浅沟槽隔离结构; 蚀刻有源区并在其上形成栅介电层和定位栅，形成垂直于定位栅的字线; 在字线的外表面上形成间隔层; 将离子注入所形成的结构中，以在所述有源区域的字线的相对侧上形成n型和p型区域; 在n型和p型区域分别形成n型和p型浮体; 形成垂直于字线并连接到n型浮体的源极线; 形成垂直于源极线并连接到p型浮体的位线。因此，实现了具有稳定阈值电压的垂直晶体管。

8. 发明申请

US20120168857A1 Memory structure having a floating body and method for fabricating the same 有权
公开(公告)号：US20120168857A1
公开(公告)日：2012-07-05
申请号：US13102039
申请日：2011-05-05
申请人： Tzung-Han Lee , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7841 , H01L27/10802 , H01L29/66666 , H01L29/7827
摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.

9. 发明授权

US07586152B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US07586152B2
公开(公告)日：2009-09-08
申请号：US11949047
申请日：2007-12-03
申请人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10891 , H01L27/10876
摘要： The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.
摘要翻译：本发明公开了一种掩埋字线的结构，其包括具有U形沟槽的半导体衬底，U形沟槽中的U形栅极介电层，U形栅极介电层上的多晶硅层，多晶硅层上的导电层和导电层上的覆盖电介质层。半导体结构可以具有最小化的尺寸，并且当由此形成凹槽时，相应地提高了积分，而不会受到短沟道效应的影响。

10. 发明授权

US07557012B2 Method for forming surface strap 有权
标题翻译：形成表带的方法
公开(公告)号：US07557012B2
公开(公告)日：2009-07-07
申请号：US11940308
申请日：2007-11-14
申请人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10867
摘要： A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.
摘要翻译：一种形成表面带的方法包括：在其基板的表面上形成具有导电连接层的深沟槽电容器和与导电层接触的导电连接层; 形成覆盖所述焊盘层和所述导电连接层的多晶硅层; 以角度进行选择性离子注入，以使多晶硅层的一部分成为未掺杂的多晶硅层; 去除未掺杂的多晶硅层以暴露部分导电连接层; 蚀刻暴露的导电连接层以形成凹部; 去除所述多晶硅层以使所述暴露的导电连接层成为导电连接带; 用绝缘材料填充凹槽以形成浅沟槽隔离; 暴露导电层; 并且选择性地去除导电层以形成与导电连接带一起形成表面带的第一导电带。

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