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1. 发明授权

US07608504B2 Memory and manufacturing method thereof 有权
标题翻译：其记忆及其制造方法
公开(公告)号：US07608504B2
公开(公告)日：2009-10-27
申请号：US11468311
申请日：2006-08-30
申请人： Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen , Yu-Tsung Lin
发明人： Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen , Yu-Tsung Lin
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.
摘要翻译：提供记忆。存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。位线设置在基板中。字线设置在基板上。字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

2. 发明申请

US20080054322A1 MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：内存及其制造方法
公开(公告)号：US20080054322A1
公开(公告)日：2008-03-06
申请号：US11468311
申请日：2006-08-30
申请人： Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen , Yu-Tsung Lin
发明人： Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen , Yu-Tsung Lin
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.
摘要翻译：提供记忆。存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。位线设置在基板中。字线设置在基板上。字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

3. 发明授权

US06448126B1 Method of forming an embedded memory 有权
标题翻译：形成嵌入式存储器的方法
公开(公告)号：US06448126B1
公开(公告)日：2002-09-10
申请号：US09682217
申请日：2001-08-07
申请人： Erh-Kun Lai , Hsin-Huei Chen , Shou-Wei Huang , Ying-Tso Chen , Chien-Hung Liu , Shyi-Shuh Pan
发明人： Erh-Kun Lai , Hsin-Huei Chen , Shou-Wei Huang , Ying-Tso Chen , Chien-Hung Liu , Shyi-Shuh Pan
IPC分类号： H01L218238
CPC分类号： H01L21/823418 , H01L21/823412
摘要： A method of forming an embedded memory integrating nitride read only memory starts by forming an ONO layer and a protective cap layer on a surface of a semiconductor substrate defined with a memory area and a periphery area. The periphery area has a first, a second and a third device area. An etching and a first ion implantation process form each bit line in the memory area. A spacer is then formed at either side of the protective cap layer and the ONO layer in the memory area, and the protective cap layer and the ONO layer are removed in the first device area. The threshold voltage for the first device area is adjusted and a first thermal oxidation process forms a buried drain oxide layer atop each bit line and a first gate oxide layer on the surface of the first device area, respectively. The protective cap layer and the ONO layer are removed from the second device area and the third device area, and a second gate oxide layer is formed in the second device area and the third device area. Finally, the protective cap layer in the memory area and the second gate oxide layer in the third device area are removed, and a third gate oxide layer is formed in the third device area.
摘要翻译：集成氮化物只读存储器的嵌入式存储器的形成方法首先通过在由存储区域和周边区域限定的半导体衬底的表面上形成ONO层和保护覆盖层。周边区域具有第一，第二和第三设备区域。蚀刻和第一离子注入工艺在存储区域中形成每个位线。然后在保护盖层和存储区域中的ONO层的任一侧形成间隔物，并且在第一装置区域中去除保护盖层和ONO层。调整第一器件区域的阈值电压，第一热氧化工艺分别在第一器件区域的表面上的每个位线和第一栅极氧化物层的顶部形成掩埋的漏极氧化物层。从第二设备区域和第三设备区域去除保护盖层和ONO层，并且在第二设备区域和第三设备区域中形成第二栅极氧化物层。最后，去除存储区域中的保护盖层和第三器件区域中的第二栅极氧化物层，并且在第三器件区域中形成第三栅极氧化物层。

4. 发明申请

US20070269943A1 Non-volatile memory and method of fabricating the same 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20070269943A1
公开(公告)日：2007-11-22
申请号：US11435458
申请日：2006-05-16
申请人： Chin-Hsien Chen , Ying-Tso Chen , Chien-Hung Liu , Shou-Wei Huang
发明人： Chin-Hsien Chen , Ying-Tso Chen , Chien-Hung Liu , Shou-Wei Huang
IPC分类号： H01L21/8234
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/7881 , H01L29/792
摘要： A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.
摘要翻译：提供了一种制造非易失性存储器的方法。首先，在基板上形成两个开口。在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

5. 发明授权

US07804122B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07804122B2
公开(公告)日：2010-09-28
申请号：US12434828
申请日：2009-05-04
申请人： Chin-Hsien Chen , Ying-Tso Chen , Chien-Hung Liu , Shou-Wei Huang
发明人： Chin-Hsien Chen , Ying-Tso Chen , Chien-Hung Liu , Shou-Wei Huang
IPC分类号： H01L31/119
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.
摘要翻译：非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫，设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。衬垫具有比衬底更低的顶表面。第二导电层具有与衬垫的顶表面共面的顶表面。第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

6. 发明授权

US06440798B1 Method of forming a mixed-signal circuit embedded NROM memory and MROM memory 有权
标题翻译：形成嵌入式NROM存储器和MROM存储器的混合信号电路的方法
公开(公告)号：US06440798B1
公开(公告)日：2002-08-27
申请号：US09682148
申请日：2001-07-26
申请人： Erh-Kun Lai , Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan , Ying-Tso Chen
发明人： Erh-Kun Lai , Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan , Ying-Tso Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： The present invention gives a method for creating a NROM memory from a semiconductor substrate. Numerous process steps are included to achieve this including forming shallow trench isolation areas, many ion implantation processes, ROM code implantation processes, photolithography and creation of layers and removal of layers. At the end of the process a mixed-signal circuit embedded NROM and NROM memory are created.
摘要翻译：本发明提供了一种从半导体衬底生成NROM存储器的方法。包括许多工艺步骤以实现这一点，包括形成浅沟槽隔离区域，许多离子注入工艺，ROM代码注入工艺，光刻以及层的创建和层的去除。在该过程结束时，创建了嵌入NROM和NROM存储器的混合信号电路。

7. 发明授权

US08809933B2 Bit line structure, semiconductor device and method of forming the same 有权
标题翻译：位线结构，半导体器件及其形成方法
公开(公告)号：US08809933B2
公开(公告)日：2014-08-19
申请号：US12834212
申请日：2010-07-12
申请人： Guan-De Lee , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
发明人： Guan-De Lee , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
IPC分类号： H01L29/788 , H01L27/115 , H01L21/74
CPC分类号： H01L27/11568 , H01L21/743
摘要： A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.
摘要翻译：提供了包括衬底，多个堆叠栅极结构，多个掺杂区域，多个衬底层，多个导电层，多个电介质层和多个字线的半导体器件。衬底中具有多个沟槽。堆叠的栅极结构在沟槽之间的衬底上。掺杂区域在沟槽的侧壁或底部的衬底中。衬垫层位于堆叠的栅极结构的侧壁的至少一部分和沟槽的侧壁上。导电层位于沟槽中并与掺杂区电连接。电介质层位于导电层之间并且在堆叠的栅极结构之间。字线在基板上并电连接到堆叠的栅极结构。

8. 发明申请

US20110198698A1 BIT LINE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：位线结构，半导体器件及其形成方法
公开(公告)号：US20110198698A1
公开(公告)日：2011-08-18
申请号：US12834212
申请日：2010-07-12
申请人： GUAN-DE LEE , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
发明人： GUAN-DE LEE , Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen
IPC分类号： H01L27/088 , H01L21/8234 , H01L23/48
CPC分类号： H01L27/11568 , H01L21/743
摘要： A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.
摘要翻译：提供了包括衬底，多个堆叠栅极结构，多个掺杂区域，多个衬底层，多个导电层，多个电介质层和多个字线的半导体器件。衬底中具有多个沟槽。堆叠的栅极结构在沟槽之间的衬底上。掺杂区域在沟槽的侧壁或底部的衬底中。衬垫层位于堆叠的栅极结构的侧壁的至少一部分和沟槽的侧壁上。导电层位于沟槽中并与掺杂区电连接。电介质层位于导电层之间并且在堆叠的栅极结构之间。字线在基板上并电连接到堆叠的栅极结构。

9. 发明授权

US07307018B2 Method of fabricating conductive lines 有权
标题翻译：制造导线的方法
公开(公告)号：US07307018B2
公开(公告)日：2007-12-11
申请号：US11236961
申请日：2005-09-27
申请人： Jui-Pin Chang , Chien-Hung Liu , Ying-Tso Chen , Shou-Wei Huang
发明人： Jui-Pin Chang , Chien-Hung Liu , Ying-Tso Chen , Shou-Wei Huang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/336 , H01L21/8234
CPC分类号： H01L23/5283 , H01L21/76834 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.
摘要翻译：形成适于降低导线的薄层电阻的导线的方法。该方法包括提供其上形成有导电层的材料层并在导电层上形成图案化掩模层的步骤。此外，通过使用图案化掩模层作为掩模去除导电层的一部分，并且在图案化掩模层和导电层的侧壁上形成间隔物。导电层的一部分被去除直到材料层暴露以形成导电线，其中间隔物和图案化掩模层用作掩模。

10. 发明申请

US20060286731A1 Method of fabricating conductive lines and structure of the same 有权
标题翻译：制造导线及其结构的方法
公开(公告)号：US20060286731A1
公开(公告)日：2006-12-21
申请号：US11236961
申请日：2005-09-27
申请人： Jui-Pin Chang , Chien-Hung Liu , Ying-Tso Chen , Shou-Wei Huang
发明人： Jui-Pin Chang , Chien-Hung Liu , Ying-Tso Chen , Shou-Wei Huang
IPC分类号： H01L21/8234 , H01L21/44 , H01L23/52
CPC分类号： H01L23/5283 , H01L21/76834 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.
摘要翻译：形成适于降低导线的薄层电阻的导线的方法。该方法包括提供其上形成有导电层的材料层并在导电层上形成图案化掩模层的步骤。此外，通过使用图案化掩模层作为掩模去除导电层的一部分，并且在图案化掩模层和导电层的侧壁上形成间隔物。导电层的一部分被去除直到材料层暴露以形成导电线，其中间隔物和图案化掩模层用作掩模。

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