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    • 1. 发明授权
    • Method for making a concave bottom oxide within a trench
    • 在沟槽内制作凹底氧化物的方法
    • US06365524B1
    • 2002-04-02
    • US09310031
    • 1999-05-11
    • Chien-Hung ChenChung-Yih ChenJerry C. S. LinYen-Rong Chang
    • Chien-Hung ChenChung-Yih ChenJerry C. S. LinYen-Rong Chang
    • H01L21302
    • H01L21/76232H01L21/31612
    • This present discloses a method for making a concave bottom oxide within a trench, the steps comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; defining the insulating layer to form an opening exposing the surface of the semiconductor substrate; dry-etching the exposed semiconductor substrate within the opening by using the first insulating layer as an etching mask to form a trench; depositing a first oxide layer conformably over the insulating layer, the side-walls and the bottom of the trench; depositing a second oxide layer on the first oxide layer and filling-up the trench surrounded by the first oxide layer; annealing to densify the first and second oxide layers; etching-back the first and second oxide layer to remove the portion overlying the first insulating layer, and forming a spacer consisting of the residual first oxide layer on the side-walls of the trench, and a concave bottom oxide consisting of the first and second oxide layers on the bottom of the trench.
    • 本发明公开了一种在沟槽内制造凹底氧化物的方法,所述步骤包括:提供半导体衬底; 在半导体衬底上形成绝缘层; 限定所述绝缘层以形成暴露所述半导体衬底的表面的开口; 通过使用第一绝缘层作为蚀刻掩模对开口内的暴露的半导体衬底进行干蚀刻以形成沟槽; 在绝缘层,沟槽的侧壁和底部上顺应地沉积第一氧化物层; 在所述第一氧化物层上沉积第二氧化物层并填充由所述第一氧化物层包围的所述沟槽; 退火以使第一和第二氧化物层致密化; 蚀刻第一和第二氧化物层以除去覆盖第一绝缘层的部分,以及在沟槽的侧壁上形成由残留的第一氧化物层组成的间隔物和由第一和第二氧化物组成的凹底氧化物 沟槽底部的氧化物层。
    • 5. 发明授权
    • Signal controlling method for 3D image display device
    • 3D图像显示装置的信号控制方法
    • US08848115B2
    • 2014-09-30
    • US12954869
    • 2010-11-27
    • Shih-Chieh LinHsiang-Tan LinChien-Hung ChenChun-Chieh Chiu
    • Shih-Chieh LinHsiang-Tan LinChien-Hung ChenChun-Chieh Chiu
    • G02F1/1335H04N13/02G02B27/26H04N13/04
    • G02B27/26H04N13/337
    • The present invention provides a 3D image signal controlling method. The method comprises inputting a left eye image into the first liquid crystal layer, turning off the backlight module and switching gray levels of the second liquid crystal layer to a minimum gray level during (4N−3)th time interval, wherein N is natural number; stopping inputting the left eye image, turning on the backlight module and remaining the gray levels of the second liquid crystal layer as the minimum gray level during (4N−2)th time interval; inputting a right eye image into the first liquid crystal layer, turning off the backlight module and switching the gray levels of the second liquid crystal layer as a maximum gray level during (4N−1)th time interval; and stopping inputting the right eye image, turning on the backlight module and remaining the gray levels of the second liquid crystal layer as the maximum gray level during (4N)th time interval.
    • 本发明提供一种3D图像信号控制方法。 该方法包括在(4N-3)时间间隔期间将左眼图像输入到第一液晶层中,关闭背光模块并将第二液晶层的灰度级切换到最小灰度级,其中N是自然数 ; 停止输入左眼图像,在(4N-2)时间间隔期间打开背光模块并保持第二液晶层的灰度级为最小灰度级; 在第(4N-1)次间隔期间,将右眼图像输入到第一液晶层中,关闭背光模块并将第二液晶层的灰度级切换为最大灰度级; 停止输入右眼图像,在(4N)时间间隔期间打开背光模块并保持第二液晶层的灰度级为最大灰度级。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION
    • 半导体器件特征密度梯度验证
    • US20130198710A1
    • 2013-08-01
    • US13362914
    • 2012-01-31
    • Young-Chow PengChung-Hui ChenChien-Hung ChenPo-Zeng Kang
    • Young-Chow PengChung-Hui ChenChien-Hung ChenPo-Zeng Kang
    • G06F17/50
    • G06F17/5081G03F1/36G03F1/70
    • A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
    • 提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。 该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。 设备布局包括各种设备区域,并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较,并且还用于确定设备特征密度的梯度。 可以从特定设备区域到周围区域监视梯度。 用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。
    • 9. 发明授权
    • Method of manufacturing flash memory device
    • 制造闪存设备的方法
    • US08486781B2
    • 2013-07-16
    • US12755418
    • 2010-04-07
    • Chih-Jen HuangChien-Hung Chen
    • Chih-Jen HuangChien-Hung Chen
    • H01L21/336
    • H01L27/11521
    • A method of manufacturing flash memory device is provided and includes the following steps. First, a substrate is provided. Then, a stacked gate structure is formed on the substrate. Subsequently, a first oxide layer is formed on the stacked gate structure. Following that, a nitride spacer is formed on the first oxide layer, wherein a nitrogen atom-introducing treatment is performed after the forming of the first oxide layer and before the forming of the nitride spacer. Accordingly, the nitrogen atom-introducing treatment of the presentation invention can improve the data retention reliability of the flash memory device.
    • 提供了一种制造闪速存储器件的方法,包括以下步骤。 首先,提供基板。 然后,在基板上形成层叠栅极结构。 随后,在堆叠的栅极结构上形成第一氧化物层。 接着,在第一氧化物层上形成氮化物间隔物,在形成第一氧化物层之后,在形成氮化物间隔物之前,进行氮原子导入处理。 因此,本发明的氮原子引入处理可以提高闪速存储装置的数据保持可靠性。