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1. 发明申请

US20130244139A1 Reflective Lithography Masks and Systems and Methods 有权
标题翻译：反光光刻面具及系统与方法
公开(公告)号：US20130244139A1
公开(公告)日：2013-09-19
申请号：US13421113
申请日：2012-03-15
申请人： Chien-Hsuan Liu , Jen-Pan Wang
发明人： Chien-Hsuan Liu , Jen-Pan Wang
IPC分类号： G03F1/52 , G03F7/20 , G03B27/54
CPC分类号： G03F1/52 , G03F1/24 , G03F1/50 , G03F1/76 , G03F7/70058 , G03F7/70283 , G03F7/703
摘要： Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.
摘要翻译：公开了各种非平面反射光刻掩模，使用这种光刻掩模的系统和方法。一个实施例是包括透明基板，反射材料和掩模版图案的光刻掩模。透明基板包括弯曲表面。反射材料与透明基板的弯曲表面相邻，并且反射材料和透明基板之间的界面是反射表面。标线图案位于透明基板的第二表面上。标线图案的反射率小于反射材料的反射率。公开了形成类似光刻掩模和使用类似光刻掩模的方法。

2. 发明授权

US08772054B2 Focus control method for photolithography 有权
标题翻译：光刻对焦控制方法
公开(公告)号：US08772054B2
公开(公告)日：2014-07-08
申请号：US13227805
申请日：2011-09-08
申请人： Jen-Pan Wang , Chien-Hsuan Liu , Ching-Hsien Chen , Chao-Chi Chen
发明人： Jen-Pan Wang , Chien-Hsuan Liu , Ching-Hsien Chen , Chao-Chi Chen
IPC分类号： H01L21/66
CPC分类号： G03F7/70641 , G03F7/70341 , G03F9/7026 , G03F9/7034 , G03F9/7053
摘要： A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
摘要翻译：一种方法包括提供在衬底上具有至少一层材料的半导体衬底。对基板施加声音，使得声波被材料层的顶表面反射。使用传感器检测声波。基于检测到的声波来确定顶面的形貌。确定的地形用于控制浸没光刻工艺。

3. 发明授权

US08735024B2 Non-planar lithography mask and system and methods 有权
标题翻译：非平面光刻掩模及系统及方法
公开(公告)号：US08735024B2
公开(公告)日：2014-05-27
申请号：US13421235
申请日：2012-03-15
申请人： Chien-Hsuan Liu , Jen-Pan Wang
发明人： Chien-Hsuan Liu , Jen-Pan Wang
IPC分类号： G03F7/24 , G03F1/50
CPC分类号： G03F1/50 , G03F7/70283 , G03F7/703
摘要： Various non-planar lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a lens-type transparent substrate and a reticle pattern on a surface of the lens-type transparent substrate. The reticle pattern is opaque to optical radiation. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.
摘要翻译：公开了各种非平面光刻掩模，使用这种光刻掩模的系统和方法。实施例是在透镜型透明基板的表面上包括透镜型透明基板和标线图案的光刻掩模。标线图案对于光学辐射是不透明的。公开了形成类似光刻掩模和使用类似光刻掩模的方法。

4. 发明授权

US08802333B2 Reflective lithography masks and systems and methods 有权
标题翻译：反光光刻面具及系统及方法
公开(公告)号：US08802333B2
公开(公告)日：2014-08-12
申请号：US13421113
申请日：2012-03-15
申请人： Chien-Hsuan Liu , Jen-Pan Wang
发明人： Chien-Hsuan Liu , Jen-Pan Wang
IPC分类号： G03F1/00
CPC分类号： G03F1/52 , G03F1/24 , G03F1/50 , G03F1/76 , G03F7/70058 , G03F7/70283 , G03F7/703
摘要： Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.
摘要翻译：公开了各种非平面反射光刻掩模，使用这种光刻掩模的系统和方法。一个实施例是包括透明基板，反射材料和掩模版图案的光刻掩模。透明基板包括弯曲表面。反射材料与透明基板的弯曲表面相邻，并且反射材料和透明基板之间的界面是反射表面。标线图案位于透明基板的第二表面上。标线图案的反射率小于反射材料的反射率。公开了形成类似光刻掩模和使用类似光刻掩模的方法。

5. 发明申请

US20130244140A1 Non-Planar Lithography Mask and System and Methods 有权
标题翻译：非平面光刻面具及系统与方法
公开(公告)号：US20130244140A1
公开(公告)日：2013-09-19
申请号：US13421235
申请日：2012-03-15
申请人： Chien-Hsuan Liu , Jen-Pan Wang
发明人： Chien-Hsuan Liu , Jen-Pan Wang
IPC分类号： G03F7/20 , G03B27/54 , G03F1/00
CPC分类号： G03F1/50 , G03F7/70283 , G03F7/703
摘要： Various non-planar lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a lens-type transparent substrate and a reticle pattern on a surface of the lens-type transparent substrate. The reticle pattern is opaque to optical radiation. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.
摘要翻译：公开了各种非平面光刻掩模，使用这种光刻掩模的系统和方法。实施例是在透镜型透明基板的表面上包括透镜型透明基板和标线图案的光刻掩模。标线图案对于光学辐射是不透明的。公开了形成类似光刻掩模和使用类似光刻掩模的方法。

6. 发明授权

US06284557B1 Optical sensor by using tunneling diode 有权
标题翻译：光传感器采用隧道二极管
公开(公告)号：US06284557B1
公开(公告)日：2001-09-04
申请号：US09414928
申请日：1999-10-12
申请人： Ho-Yin Yiu , Chein-Ling Jan , Jen-Pan Wang , Lin-June Wu
发明人： Ho-Yin Yiu , Chein-Ling Jan , Jen-Pan Wang , Lin-June Wu
IPC分类号： H01L2100
CPC分类号： H01L31/0352 , H01L31/102 , Y10S438/979
摘要： A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.
摘要翻译：提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型层在绝缘层上。优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

7. 发明授权

US08962353B2 System and methods for semiconductor device performance prediction during processing 有权
标题翻译：处理过程中半导体器件性能预测的系统和方法
公开(公告)号：US08962353B2
公开(公告)日：2015-02-24
申请号：US13234964
申请日：2011-09-16
申请人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
发明人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/12
摘要： Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.
摘要翻译：用于在处理过程中预测半导体器件性能标准的方法和系统。描述了一种包括接收半导体晶片的方法; 在形成有源器件的半导体晶片上执行半导体处理，其在完成时将呈现器件性能标准; 在半导体处理期间，测量至少一个器件性能标准相关的物理参数; 使用所述至少一个在线测量来估计所述有源器件的器件性能标准的估计值，并使用对应于后续半导体处理步骤的器件性能标准相关物理参数的估计测量值; 将设备性能标准的估计值与可接受范围进行比较; 以及基于所述比较来确定所述半导体晶片上的有源器件是否将器件性能标准在可接受的范围内。描述了一种用于处理半导体晶片的系统，其包括用于执行该方法的可编程处理器。

8. 发明授权

US08648341B2 Methods and apparatus for testing pads on wafers 有权
标题翻译：在晶片上测试垫的方法和设备
公开(公告)号：US08648341B2
公开(公告)日：2014-02-11
申请号：US13403880
申请日：2012-02-23
申请人： Chung-Yuan Yang , Jen-Pan Wang , Jiun-Jie Huang
发明人： Chung-Yuan Yang , Jen-Pan Wang , Jiun-Jie Huang
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L22/34
摘要： Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.
摘要翻译：公开了在模具的多层内共享测试功能块之间的测试焊盘的方法和装置。半导体晶片包括由划线分开的第一管芯和第二管芯。第一垫，第二垫和第三垫位于划线中。测试垫也可以位于模具内。第一焊盘和第二焊盘用于测试第一层内的第一功能块，并且第一焊盘和第三焊盘用于测试第一裸片的第二层内的第二功能块。共享的第一个测试焊盘用于测试包含在芯片的不同层中的多个功能块。因此，需要更少的测试焊盘，这导致晶片中划线的面积减小。

9. 发明申请

US20130221353A1 Methods and Apparatus for Testing Pads on Wafers 有权
标题翻译：在硅片上测试垫的方法和装置
公开(公告)号：US20130221353A1
公开(公告)日：2013-08-29
申请号：US13403880
申请日：2012-02-23
申请人： Chung-Yuan Yang , Jen-Pan Wang , Jiun-Jie Huang
发明人： Chung-Yuan Yang , Jen-Pan Wang , Jiun-Jie Huang
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L22/34
摘要： Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer.
摘要翻译：公开了在模具的多层内共享测试功能块之间的测试焊盘的方法和装置。半导体晶片包括由划线分开的第一管芯和第二管芯。第一垫，第二垫和第三垫位于划线中。测试垫也可以位于模具内。第一焊盘和第二焊盘用于测试第一层内的第一功能块，并且第一焊盘和第三焊盘用于测试第一裸片的第二层内的第二功能块。共享的第一个测试焊盘用于测试包含在芯片的不同层中的多个功能块。因此，需要更少的测试焊盘，这导致晶片中划线的面积减小。

10. 发明申请

US20130071957A1 System and Methods for Semiconductor Device Performance Prediction During Processing 有权
标题翻译：半导体器件性能预测的系统和方法
公开(公告)号：US20130071957A1
公开(公告)日：2013-03-21
申请号：US13234964
申请日：2011-09-16
申请人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
发明人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/12
摘要： Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.
摘要翻译：用于在处理过程中预测半导体器件性能标准的方法和系统。描述了一种包括接收半导体晶片的方法; 在形成有源器件的半导体晶片上执行半导体处理，其在完成时将呈现器件性能标准; 在半导体处理期间，测量至少一个器件性能标准相关的物理参数; 使用所述至少一个在线测量来估计所述有源器件的器件性能标准的估计值，并使用对应于后续半导体处理步骤的器件性能标准相关物理参数的估计测量值; 将设备性能标准的估计值与可接受范围进行比较; 以及基于所述比较来确定所述半导体晶片上的有源器件是否将器件性能标准在可接受的范围内。描述了一种用于处理半导体晶片的系统，其包括用于执行该方法的可编程处理器。

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