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1. 发明授权

US07790505B2 Semiconductor chip package manufacturing method and structure thereof 有权
标题翻译：半导体芯片封装制造方法及其结构
公开(公告)号：US07790505B2
公开(公告)日：2010-09-07
申请号：US11871319
申请日：2007-10-12
申请人： Chian-Chi Lin , Chih-Huang Chang , Yueh-Lung Lin
发明人： Chian-Chi Lin , Chih-Huang Chang , Yueh-Lung Lin
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L2224/02371 , H01L2924/15311
摘要： A semiconductor chip package manufacturing method and a structure thereof are provided. The manufacturing method includes: providing a base having an image sensor chip and an encapsulant, in which the image sensor chip has pads and an active area; placing a transparent insulator on the active area; forming an insulation layer on an upper surface of the base; opening a plurality of openings to expose the pads; forming a plurality of through holes penetrating the insulation layer and the encapsulant outside of the image sensor chips; forming a metal layer on surfaces of the insulation layer, the openings, the pads and the through holes, and on a lower surface of the base, so as to extend the pads to the lower surface of the base; patterning the metal layer to expose a top area of the transparent insulator and remove a partial area of the metal layer on the lower surface of the base to form contacts; and sawing the base to form a package structure containing a single image sensor chip.
摘要翻译：提供半导体芯片封装的制造方法及其结构。该制造方法包括：提供具有图像传感器芯片和密封剂的基座，其中图像传感器芯片具有焊盘和有源区域; 在有源区域放置透明绝缘体; 在所述基座的上表面上形成绝缘层; 打开多个开口以露出所述垫; 在所述图像传感器芯片外部形成穿过所述绝缘层和所述密封剂的多个通孔; 在绝缘层，开口，焊盘和通孔的表面上以及在基底的下表面上形成金属层，以将焊盘延伸到基座的下表面; 图案化金属层以暴露透明绝缘体的顶部区域并去除基底的下表面上的金属层的部分区域以形成接触; 并锯切基底以形成包含单个图像传感器芯片的封装结构。

2. 发明申请

US20050023667A1 Multi-chips module package and manufacturing method thereof 有权
标题翻译：多芯片模块封装及其制造方法
公开(公告)号：US20050023667A1
公开(公告)日：2005-02-03
申请号：US10900089
申请日：2004-07-28
申请人： Chian-Chi Lin , Chih-Huang Chang
发明人： Chian-Chi Lin , Chih-Huang Chang
IPC分类号： H01L23/31 , H01L23/495
CPC分类号： H01L24/16 , H01L23/3107 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/16245 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/4911 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A multi-chips module package comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. The lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads. The first chip is placed on the lead frame and electrically connected to the lead frame through the bumps connecting the bump-bonding pads and the chip pads and the first leads; the second chip is placed over the first chip and electrically connected to the lead frame through the wires connecting the wire-bonding pads to the second leads; and the encapsulation covers the first chip, the second chip, the lead frame, and the wires. In such a manner, it not only reduces the distance of transmitting the electrical signals from chips to the outside but also it can save cost due to the lead frame manufactured by a simple manufacturing processes. In addition, a manufacturing method of the multi-chips module package is provided.
摘要翻译：多芯片模块封装包括引线框，第一芯片，第二芯片，多根导电线和封装。引线框架具有连接到第一引线的多个第一引线，第二引线和芯片焊盘。第一芯片放置在引线框架上，并通过连接凸块焊盘和芯片焊盘和第一引线的凸块电连接到引线框架; 第二芯片放置在第一芯片上并且通过将引线接合焊盘连接到第二引线的电线电连接到引线框架; 并且封装覆盖第一芯片，第二芯片，引线框架和电线。以这种方式，不仅减少了将电信号从芯片传输到外部的距离，而且还可以通过简单制造工艺制造的引线框架节省成本。此外，提供了多芯片模块封装的制造方法。

3. 发明授权

US07221041B2 Multi-chips module package and manufacturing method thereof 有权
标题翻译：多芯片模块封装及其制造方法
公开(公告)号：US07221041B2
公开(公告)日：2007-05-22
申请号：US10900089
申请日：2004-07-28
申请人： Chian-Chi Lin , Chih-Huang Chang
发明人： Chian-Chi Lin , Chih-Huang Chang
IPC分类号： H01L23/495
CPC分类号： H01L24/16 , H01L23/3107 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/16245 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/4911 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A multi-chips module package comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. The lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads. The first chip is placed on the lead frame and electrically connected to the lead frame through the bumps connecting the bump-bonding pads and the chip pads and the first leads; the second chip is placed over the first chip and electrically connected to the lead frame through the wires connecting the wire-bonding pads to the second leads; and the encapsulation covers the first chip, the second chip, the lead frame, and the wires. In such a manner, it not only reduces the distance of transmitting the electrical signals from chips to the outside but also it can save cost due to the lead frame manufactured by a simple manufacturing processes. In addition, a manufacturing method of the multi-chips module package is provided.
摘要翻译：多芯片模块封装包括引线框，第一芯片，第二芯片，多根导电线和封装。引线框架具有连接到第一引线的多个第一引线，第二引线和芯片焊盘。第一芯片放置在引线框架上，并通过连接凸块焊盘和芯片焊盘和第一引线的凸块电连接到引线框架; 第二芯片放置在第一芯片上并且通过将引线接合焊盘连接到第二引线的电线电连接到引线框架; 并且封装覆盖第一芯片，第二芯片，引线框架和电线。以这种方式，不仅减少了将电信号从芯片传输到外部的距离，而且还可以通过简单制造工艺制造的引线框架节省成本。此外，提供了多芯片模块封装的制造方法。

4. 发明申请

US20070176269A1 Multi-chips module package and manufacturing method thereof 审中-公开
公开(公告)号：US20070176269A1
公开(公告)日：2007-08-02
申请号：US11730442
申请日：2007-04-02
申请人： Chian-Chi Lin , Chih-Huang Chang
发明人： Chian-Chi Lin , Chih-Huang Chang
IPC分类号： H01L23/495
CPC分类号： H01L24/16 , H01L23/3107 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/16245 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/4911 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A multi-chips module package comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. The lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads. The first chip is placed on the lead frame and electrically connected to the lead frame through the bumps connecting the bump-bonding pads and the chip pads and the first leads; the second chip is placed over the first chip and electrically connected to the lead frame through the wires connecting the wire-bonding pads to the second leads; and the encapsulation covers the first chip, the second chip, the lead frame, and the wires. In such a manner, it not only reduces the distance of transmitting the electrical signals from chips to the outside but also it can save cost due to the lead frame manufactured by a simple manufacturing processes. In addition, a manufacturing method of the multi-chips module package is provided.

5. 发明授权

US07446404B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07446404B2
公开(公告)日：2008-11-04
申请号：US11645177
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L23/02 , H01L23/053 , H01L23/12 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2924/01019 , H01L2924/01078 , H01L2924/00012
摘要： A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.
摘要翻译：一种三维封装，其包括具有至少一个第一焊盘的第一晶片和暴露第一焊盘的第一保护层。第一孔穿透第一晶片。第一隔离层设置在第一孔的侧壁上。第一导电层的下端在第一晶片的表面下方延伸。第一金属设置在第一孔中，并经由第一导电层与第一焊盘电连接。第一焊料设置在第一孔中的第一金属上，其中第一焊料的熔点低于第一焊料的熔点。第二晶片被配置为类似于第一晶片。第二晶片的第二导电层的下端在第二晶片的表面下方延伸并接触第一焊料的上端。

6. 发明申请

US20070172986A1 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US20070172986A1
公开(公告)日：2007-07-26
申请号：US11645177
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2924/01019 , H01L2924/01078 , H01L2924/00012
摘要： The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package structure comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. The second wafer has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. The lower end of the second conductive layer extends below the surface of the second wafer and contacts the upper end of the first solder. The second metal is disposed in the second hole and is electrically connected to the second pad via the second conductive layer. The second space is disposed on the second metal in the second hole.
摘要翻译：本发明涉及三维包装及其制造方法。三维封装结构包括第一晶片，至少一个第一孔，第一隔离层，第一导电层，第一金属，第一焊料，第二晶片，至少一个第二孔，第二隔离层，第二导电层，第二金属和第二空间。第一晶片具有至少一个第一焊盘和暴露第一焊盘的第一保护层。第一个孔穿透第一个晶片。第一隔离层设置在第一孔的侧壁上。第一导电层的下端延伸到第一晶片的表面下方。第一金属设置在第一孔中，并且经由第一导电层电连接到第一焊盘。第一焊料设置在第一孔中的第一金属上，其中第一焊料的熔点低于第一焊料的熔点。第二晶片具有至少一个第二焊盘和暴露第二焊盘的第二保护层。第二孔穿透第二晶片。第二隔离层设置在第二孔的侧壁上。第二导电层的下端延伸到第二晶片的表面下方并接触第一焊料的上端。第二金属设置在第二孔中，并通过第二导电层与第二焊盘电连接。第二空间设置在第二孔中的第二金属上。

7. 发明授权

US08288853B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US08288853B2
公开(公告)日：2012-10-16
申请号：US12615852
申请日：2009-11-10
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05647 , H01L2224/05666 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05099
摘要： A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.
摘要翻译：封装包括包括半导体本体，孔，隔离层，导电层和焊料的第一单元。半导体本体具有第一表面，其具有衬垫和暴露衬垫的保护层。孔穿透半导体本体。隔离层设置在孔的侧壁上。导电层覆盖焊盘，保护层的一部分和隔离层。导电层的下端延伸到半导体本体的第二表面的下方。焊料设置在孔中，并通过导电层与焊盘电连接。类似于第一单元并且堆叠在其上的第二单元包括延伸到第二半导体本体的第二表面下方并接触第一焊料的上端的第二导电层的下端。

8. 发明授权

US07642132B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07642132B2
公开(公告)日：2010-01-05
申请号：US11584546
申请日：2006-10-23
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/44
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05647 , H01L2224/05666 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05099
摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
摘要翻译：本发明涉及三维包装及其制造方法。该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少加入后三维包装的整体高度。

9. 发明授权

US07528053B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07528053B2
公开(公告)日：2009-05-05
申请号：US11645042
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/46 , H01L21/4763
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2924/01019 , H01L2924/01078 , H01L2924/00012
摘要： A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.
摘要翻译：三维封装及其制造方法，包括提供晶片; 在晶片中形成至少一个盲孔; 在盲孔的侧壁上形成隔离层; 在隔离层上形成导电层; 在导电层上形成干膜; 用金属填充盲孔; 去除干膜，图案化导电层; 去除盲孔中的金属的一部分以形成空间; 去除所述晶片的所述第二表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; 在导电层的下端形成焊料，焊料的熔点低于金属; 堆叠多个晶片，并进行回流处理; 并切割堆叠的晶片，以形成三维封装。

10. 发明申请

US20070090507A1 Multi-chip package structure 审中-公开
标题翻译：多芯片封装结构
公开(公告)号：US20070090507A1
公开(公告)日：2007-04-26
申请号：US11332293
申请日：2006-01-17
申请人： Chian-Chi Lin , Cheng-Yin Lee
发明人： Chian-Chi Lin , Cheng-Yin Lee
IPC分类号： H01L23/02
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/3135 , H01L23/49833 , H01L23/4985 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/8592 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2225/06589 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip package structure includes a first substrate, a first chip, a sub-package, and a first molding compound. The first substrate has a first surface and a second surface. The first chip is attached to the first surface of the first substrate by flip-chip bonding so as to reduce a step of wire bonding and reduce the total height of the package structure. The sub-package includes a second substrate, a second chip, and a second molding compound. The second substrate has a first surface and a second surface. The second substrate is a flexible substrate and is directly connected to the first surface of the first substrate so as to reduce another step of wire bonding.
摘要翻译：多芯片封装结构包括第一衬底，第一芯片，子封装和第一模塑料。第一基板具有第一表面和第二表面。第一芯片通过倒装芯片接合附接到第一基板的第一表面，以减少引线接合的步骤并降低封装结构的总高度。子组件包括第二衬底，第二芯片和第二模塑料。第二基板具有第一表面和第二表面。第二基板是柔性基板，并且直接连接到第一基板的第一表面，以便减少引线接合的另一步骤。

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