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1. 发明授权

US06468870B1 Method of fabricating a LDMOS transistor 有权
标题翻译：制造LDMOS晶体管的方法
公开(公告)号：US06468870B1
公开(公告)日：2002-10-22
申请号：US09747137
申请日：2000-12-26
申请人： Chi-Hung Kao , Shih-Hui Chen , Tsung-Yi Huang , Jeng Gong , Kuo-Shu Huang
发明人： Chi-Hung Kao , Shih-Hui Chen , Tsung-Yi Huang , Jeng Gong , Kuo-Shu Huang
IPC分类号： H01L21336
CPC分类号： H01L29/7816 , H01L21/28194 , H01L21/28238 , H01L29/0696 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/66681 , H01L29/7801
摘要： A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the low voltage well. In a key step, a dielectric block is formed over the bird beaks of the field oxide regions. A gate is formed over the dielectric block. After this the LDMOS device is completed. The invention's dielectric block covers the bird's beaks of the field oxide regions and enhances the e-field tolerance. The invention's e-field enhancement dielectric block relieves the e-field near the bird's beak, thus increasing the breakdown voltage of the transistor.
摘要翻译：一种在栅电极下方具有介电块的LDHOS晶体管的制造方法。高压阱，低电压阱（LV PW）和具有鸟嘴的场氧化物区域设置在衬底中，并且将高电压阱和低电压阱重叠。在关键步骤中，在场氧化物区域的鸟喙上形成介电块。在介质块上方形成栅极。之后，LDMOS设备完成。本发明的介电块覆盖了场氧化物区域的鸟嘴，增强了电场容差。本发明的电场增强介质块缓解了鸟嘴附近的电场，从而增加了晶体管的击穿电压。

2. 发明授权

US06734493B2 Lateral double diffused metal oxide semiconductor (LDMOS) device with aligned buried layer isolation layer 有权
标题翻译：具有对准埋层隔离层的横向双扩散金属氧化物半导体（LDMOS）器件
公开(公告)号：US06734493B2
公开(公告)日：2004-05-11
申请号：US10071431
申请日：2002-02-08
申请人： Shih-Hui Chen , Chi-Hung Kao , Jeng Gong , Kuo-Hsu Huang , Meng-Chi Wu , Jia-Rong Yu
发明人： Shih-Hui Chen , Chi-Hung Kao , Jeng Gong , Kuo-Hsu Huang , Meng-Chi Wu , Jia-Rong Yu
IPC分类号： H01L2972
CPC分类号： H01L29/1083 , H01L29/7835
摘要： Within both a lateral double diffused metal oxide semiconductor (LDMOS) device, and a method for fabrication thereof, there is formed a buried layer of polarity equivalent with a well region within which is formed a drain region. The buried layer is formed laterally aligned with respect to the well region, and separated therefrom by a portion of an epitaxial layer. The lateral double diffused metal oxide semiconductor (LDMOS) device exhibits enhanced electrical performance.
摘要翻译：在横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法中，形成了与阱区极性等效的掩埋层，在其中形成漏极区。掩埋层相对于阱区横向对齐形成，并由外延层的一部分与之分离。横向双扩散金属氧化物半导体（LDMOS）器件表现出增强的电性能。

3. 发明授权

US06292393B1 Method for extracting substrate coupling coefficient of a flash memory 有权
标题翻译：提取闪速存储器的衬底耦合系数的方法
公开(公告)号：US06292393B1
公开(公告)日：2001-09-18
申请号：US09531197
申请日：2000-03-20
申请人： Jung-Yu Tsai , Chih-Mu Huang , Chi-Hung Kao , Chuan-Jane Chao
发明人： Jung-Yu Tsai , Chih-Mu Huang , Chi-Hung Kao , Chuan-Jane Chao
IPC分类号： G11C700
CPC分类号： G11C16/20
摘要： A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg. Similarly, keeping the drain voltage Vd and the source voltage Vs fixed and varying the control gate voltage Vcg and the substrate voltage Vb, a third coefficient ratio of the substrate coupling coefficient &agr;b to the gate coupling coefficient &agr;cg, that is, &agr;b/&agr;cg. The first coefficient ratio &agr;d/&agr;cg, the second coefficient ratio &agr;s/&agr;cg, and the third coefficient ratio &agr;b/&agr;cg incorporate a normalization equation of &agr;d+&agr;s+&agr;b+&agr;cg=1, so that all four coefficients &agr;d, &agr;s, &agr;b, and &agr;cg can be exactly solved.
摘要翻译：一种方法用于通过GIDL方式完全提取闪存单元的耦合系数。闪存单元由衬底，漏极区域，源极区域，控制栅极和浮动栅极组成。该方法保持源极电压Vs和衬底电压Vb固定。漏极电压Vd和控制栅极电压变化。然后，测量GIDL电流获得排水耦合系数ad与门耦合alphacg的第一系数比，即alphad / alphacg。类似地，保持漏极电压Vd和衬底电压Vb固定并改变源极电压Vs和控制栅极电压Vcg，源耦合系数αα的第二系数比与门耦合系数alphacg，即alphas / alphacg。类似地，保持漏极电压Vd和源极电压Vs固定，并且改变控制栅极电压Vcg和衬底电压Vb，衬底耦合系数alphab与栅极耦合系数alphacg的第三系数比，即alphab / alphacg。第一系数比alphad / alphacg，第二系数比alphas / alphacg和第三系数比alphab / alphacg包含alphad + alphas + alphab + alphacg = 1的归一化方程，使得所有四个系数alphad，alphas，alphab，和alphacg可以精确解决。

4. 发明申请

US20080122784A1 COMMUNICATING SYSTEM AND METHOD THEREOF 有权
标题翻译：传播系统及其方法
公开(公告)号：US20080122784A1
公开(公告)日：2008-05-29
申请号：US11557596
申请日：2006-11-08
申请人： Chih-Tao Hsieh , Fu-Chin Shen , Chi-Hung Kao
发明人： Chih-Tao Hsieh , Fu-Chin Shen , Chi-Hung Kao
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G2370/24
摘要： A communicating system suitable for a repeater and communicating method thereof are described. The communicating system comprises a receiving unit, a delay module, a transmitting unit and a control unit. The receiving unit transmits a first signal based on a KB/MS input signal. The delay module is coupled to the receiving unit and delays the first signal from the receiving unit in order to generate a second signal. The second signal has a first phase difference in comparison with the first signal. The transmitting unit is coupled to the delay module and the control unit. The transmitting unit transmits a KB/MS output signal based on the second signal while the control unit controls the transmitting unit via a control signal. Specifically, the control unit is coupled to the receiving unit, the delay module and the transmitting unit such that the control unit generates the control signal based on the first signal from the receiving unit and controls the transmitting unit by inputting the control signal into the transmitting unit. That is, the control signal of the control unit triggers the transmitting unit to dominate output control of the delayed second signal of transmitting unit. The control signal generated by the control unit has a second phase difference in comparison with the first signal.
摘要翻译：描述适用于中继器的通信系统及其通信方法。通信系统包括接收单元，延迟模块，发送单元和控制单元。接收单元基于KB / MS输入信号发送第一信号。延迟模块耦合到接收单元并延迟来自接收单元的第一信号，以便产生第二信号。第二信号与第一信号相比具有第一相位差。发送单元耦合到延迟模块和控制单元。当控制单元通过控制信号控制发送单元时，发送单元基于第二信号发送KB / MS输出信号。具体地，控制单元耦合到接收单元，延迟模块和发送单元，使得控制单元基于来自接收单元的第一信号生成控制信号，并通过将控制信号输入到发送单元中来控制发送单元单元。也就是说，控制单元的控制信号触发发送单元来控制发送单元的延迟的第二信号的输出控制。由控制单元生成的控制信号与第一信号相比具有第二相位差。

5. 发明申请

US20070200858A1 KVM switch and a computer switching method 审中-公开
标题翻译： KVM切换和电脑切换方式
公开(公告)号：US20070200858A1
公开(公告)日：2007-08-30
申请号：US11362730
申请日：2006-02-28
申请人： Chih-Iao Hsieh , Chi-Hung Kao , Chin-Chou Lin
发明人： Chih-Iao Hsieh , Chi-Hung Kao , Chin-Chou Lin
IPC分类号： G06F15/80
CPC分类号： G06F3/14 , G09G5/006 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2370/24
摘要： A KVM switch has a switching device, a first computer video interface, a second computer video interface, an image processing unit, and at least one console video interface. The switching device is arranged to select a first computing device and a second computing device from the computing devices. The first computer video interface is arranged to receive a first image from the first computing device, and the second computer video interface is arranged to receive a second image from the second computing device. The image processing unit is arranged to compose the first image and the second image to be a synthesized image. The console video interface is arranged to output one of the first image, the second image and the synthesized image to the set of user interface devices.
摘要翻译： KVM切换器具有开关装置，第一计算机视频接口，第二计算机视频接口，图像处理单元和至少一个控制台视频接口。交换设备被布置成从计算设备选择第一计算设备和第二计算设备。第一计算机视频接口被布置成从第一计算设备接收第一图像，并且第二计算机视频接口被布置为从第二计算设备接收第二图像。图像处理单元被配置为将第一图像和第二图像组成为合成图像。控制台视频接口被布置为将第一图像，第二图像和合成图像中的一个输出到用户界面设备的集合。

6. 发明申请

US20080179614A1 LIGHT-EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：发光二极管封装及其制造方法
公开(公告)号：US20080179614A1
公开(公告)日：2008-07-31
申请号：US11945902
申请日：2007-11-27
申请人： Horng-Jou Wang , Chi-Hung Kao , Huang-Kun Chen
发明人： Horng-Jou Wang , Chi-Hung Kao , Huang-Kun Chen
IPC分类号： H01L33/00
CPC分类号： H01L33/54 , H01L33/44 , H01L33/64 , H01L2933/0091
摘要： A light-emitting diode (LED) package includes a thermal-conducting substrate, a LED element, a package body, and an optical modulation device. The LED element is formed on the thermal-conducting substrate. The package body is formed on the LED element and the thermal-conducting substrate, and the optical modulation device is disposed on a light outputting surface of the package body and has a plurality of stepped protrusions for adjusting a shape of an optical field of the light beam. The optical modulation device and the package body can be two separate components and be connected together, or the optical modulation device and the package body can be integrally formed as a single piece when they are made. In addition, a manufacturing method of the LED package is also disclosed.
摘要翻译：发光二极管（LED）封装包括导热基板，LED元件，封装体和光调制装置。 LED元件形成在导热基板上。封装体形成在LED元件和导热基板上，光调制装置设置在封装体的光输出面上，并且具有多个阶梯状突起，用于调整光的光场的形状光束。光调制装置和封装体可以是两个分离的部件并连接在一起，或者当制造光调制装置和封装主体时可以一体地形成为单件。此外，还公开了LED封装的制造方法。

7. 发明授权

US07358817B2 Linearized bias circuit with adaptation 有权
标题翻译：具有适应性的线性化偏置电路
公开(公告)号：US07358817B2
公开(公告)日：2008-04-15
申请号：US11397620
申请日：2006-04-05
申请人： Chi-Hung Kao , Chih-Wei Chen , Cheng-Min Lin , Yun-Shan Chang , Shyh-Chyi Wong
发明人： Chi-Hung Kao , Chih-Wei Chen , Cheng-Min Lin , Yun-Shan Chang , Shyh-Chyi Wong
IPC分类号： H03F3/04
CPC分类号： H03F1/301 , H03F1/302 , H03F3/04 , H03F3/189 , H03F2200/372 , H03F2200/391
摘要： A linearized bias circuit with adaptation resolves the problem happening to the power amplifier with conventional bias circuit that the DC and AC characteristics of the power amplifier shift or even deteriorate due to a temperature variation. The linearized bias circuit with adaptation has a reference voltage source, a first voltage source, a first resistor, a second resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor. The present invention has the characteristics of bias current temperature compensation, gain and phase compensations to achieve high linearity for the conventional power amplifier and reducing the DC consumption power. At the same time, the quantity of the required elements and layout area in the present invention are small so that the design complexity can be reduced for improving yield, reducing IC layout area, and reducing cost.
摘要翻译：具有适应性的线性化偏置电路利用常规偏置电路解决功率放大器发生的问题，功率放大器的DC和AC特性由于温度变化而偏移甚至劣化。具有自适应的线性化偏置电路具有参考电压源，第一电压源，第一电阻器，第二电阻器，第一NPN晶体管，第二NPN晶体管和第三NPN晶体管。本发明具有偏置电流温度补偿，增益和相位补偿的特点，可实现传统功率放大器的高线性度，降低直流消耗功率。同时，本发明所需元件的数量和布局面积小，从而可以降低设计复杂度，从而提高产量，降低IC布局面积，降低成本。

8. 发明授权

US06541325B2 Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby 失效
公开(公告)号：US06541325B2
公开(公告)日：2003-04-01
申请号：US10136118
申请日：2002-05-01
申请人： Chih-Mu Huang , Chuan-Jane Chao , Chi-Hung Kao
发明人： Chih-Mu Huang , Chuan-Jane Chao , Chi-Hung Kao
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L27/0635
摘要： The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

9. 发明授权

US07774516B2 Communicating system and method thereof 有权
标题翻译：通信系统及其方法
公开(公告)号：US07774516B2
公开(公告)日：2010-08-10
申请号：US11557596
申请日：2006-11-08
申请人： Chih-tao Hsieh , Fu-Chin Shen , Chi-Hung Kao
发明人： Chih-tao Hsieh , Fu-Chin Shen , Chi-Hung Kao
IPC分类号： G06F3/00
CPC分类号： G09G5/006 , G09G2370/24
摘要： A communicating system suitable for a repeater and communicating method thereof are described. The communicating system comprises a receiving unit, a delay module, a transmitting unit and a control unit. The receiving unit transmits a first signal based on a KB/MS input signal. The delay module is coupled to the receiving unit and delays the first signal from the receiving unit in order to generate a second signal. The second signal has a first phase difference in comparison with the first signal. The transmitting unit is coupled to the delay module and the control unit. The transmitting unit transmits a KB/MS output signal based on the second signal while the control unit controls the transmitting unit via a control signal. Specifically, the control unit is coupled to the receiving unit, the delay module and the transmitting unit such that the control unit generates the control signal based on the first signal from the receiving unit and controls the transmitting unit by inputting the control signal into the transmitting unit. That is, the control signal of the control unit triggers the transmitting unit to dominate output control of the delayed second signal of transmitting unit. The control signal generated by the control unit has a second phase difference in comparison with the first signal.
摘要翻译：描述适用于中继器的通信系统及其通信方法。通信系统包括接收单元，延迟模块，发送单元和控制单元。接收单元基于KB / MS输入信号发送第一信号。延迟模块耦合到接收单元并延迟来自接收单元的第一信号，以便产生第二信号。第二信号与第一信号相比具有第一相位差。发送单元耦合到延迟模块和控制单元。当控制单元通过控制信号控制发送单元时，发送单元基于第二信号发送KB / MS输出信号。具体地，控制单元耦合到接收单元，延迟模块和发送单元，使得控制单元基于来自接收单元的第一信号生成控制信号，并通过将控制信号输入到发送单元中来控制发送单元单元。也就是说，控制单元的控制信号触发发送单元来控制发送单元的延迟的第二信号的输出控制。由控制单元生成的控制信号与第一信号相比具有第二相位差。

10. 发明授权

US06392285B1 Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby 有权
标题翻译：用于制造具有BiCMOS工艺的电容器器件的方法和由此形成的电容器器件
公开(公告)号：US06392285B1
公开(公告)日：2002-05-21
申请号：US09461014
申请日：1999-12-14
申请人： Chih-Mu Huang , Chuan-Jane Chao , Chi-Hung Kao
发明人： Chih-Mu Huang , Chuan-Jane Chao , Chi-Hung Kao
IPC分类号： H01L27082
CPC分类号： H01L28/40 , H01L27/0635
摘要： The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.
摘要翻译：本发明公开了一种用于制造具有BiCMOS工艺的电容器器件的简单方便的方法。根据本发明形成的电容器装置的电极是形成在外延层中的离子掺杂区域，使得电容器装置的电介质层的厚度相对于特定离子浓度降低。因此，其中形成的电容器器件具有高电容和良好的性能。

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